High-Speed Comparator Mirror Circuit for Kickback Noise Cancellation

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Solution Overview

Problem

Design and operation of comparators in high-speed interfaces for semiconductor memory devices are challenging due to issues such as kickback noise and input referred offset, which can lead to increased error rates in data transmission.

Innovation Solution

The use of mirror circuits to counteract kickback noise and offset clock signals to reduce or eliminate input referred offset in comparators, thereby improving data accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high-speed interface operations are implemented in comparators, then data transmission speed is improved, but kickback noise and input referred offset increase leading to higher error rates

Engineering Contradiction:

Improvedata transmission speedVSAvoiderror rate

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

A mirror circuit is introduced as an intermediary component connected to the comparator inputs. This mirror circuit generates kickback noise that is equal in magnitude but opposite in polarity to the noise generated by the comparator core, thereby canceling out the harmful kickback noise and reducing error rates in high-speed data transmission

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention converts the harmful kickback noise generated by the comparator into a beneficial effect by using the mirror circuit to generate opposing kickback noise. The harmful noise from the comparator core and the mirror circuit cancel each other out, transforming the noise problem into a noise-cancellation solution that improves reliability

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

2Measurement precision

If offset clock signals are used to reduce input referred offset, then measurement precision is improved, but device complexity increases

Engineering Contradiction:

Improveinput referred offsetVSAvoidclock signal generation

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The invention uses dynamic offset clock signals with different phases to control the timing of operations in the comparator and mirror circuit. By dynamically adjusting the phase relationships between clock signals (e.g., first phase for comparator precharge, second phase for mirror circuit precharge), the system achieves precise control over input referred offset while managing complexity through systematic phase management

Inventive Principle:

Principle #15Dynamics

3Reliability

If mirror circuits are added to counteract kickback noise, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improveerror rateVSAvoidcircuit structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The mirror circuit is designed as a copy of the comparator core circuitry, replicating its structure and characteristics. This copying approach allows the mirror circuit to generate kickback noise that matches the comparator's noise profile in magnitude but opposes it in polarity, achieving noise cancellation while using proven circuit designs to manage complexity

Inventive Principle:

Principle #26Copying

Data Source

PatentUS20250392298A1Comparator for high speed interface

Publication Date: 2025.12.25 SANDISK TECHNOLOGIES LLC

AI summary

An apparatus includes a mirror circuit connected to a comparator core. The comparator core is configured to compare voltages of first and second terminals at sample times determined by a first clock signal. The mirror circuit is connected to the first and second terminals and is driven by a second clock signal that is in anti-phase with the first clock signal.