Comparator Circuit Calibration for Transistor Mismatch Correction
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Solution Overview
Problem
High-frequency operations in memory circuits are adversely affected by small mismatches between input transistors due to manufacturing variations, which traditional methods fail to address effectively.
Innovation Solution
A comparator circuit with adjustment circuits and transistors that correct mismatches by adjusting the potential of control nodes using control signals, and a calibration control circuit to determine optimal adjustment signals for precise mismatch correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional methods (such as increasing the size of the differential input transistors) are used to address mismatch, then manufacturing precision may be improved, but device complexity and area increase
Solution Approach 1:
The patent segments the correction function into two independent adjustment circuits: a first adjustment circuit for correcting offset errors and a second adjustment circuit for correcting gain errors. Each circuit independently adjusts one control node, dividing the complex mismatch correction problem into simpler, manageable segments that can be calibrated separately.
Solution Approach 2:
The patent implements preliminary calibration action by using calibration control circuits to determine optimal adjustment signals before normal operation. The first calibration circuit determines a first adjustment signal to correct offset, and the second calibration circuit determines a second adjustment signal to correct gain, preparing the comparator for accurate high-frequency operation before signals are applied.
2Manufacturing precision
If transistor size is increased to reduce mismatch impact, then manufacturing precision improves, but area and power consumption increase
Solution Approach 1:
The patent changes the control parameters of existing transistors rather than increasing their physical size. By adjusting the potential of control nodes through adjustment circuits, the patent modifies electrical parameters (gate voltages) to compensate for manufacturing variations, achieving mismatch correction without increasing transistor area.
3Manufacturing precision
If transistor size is increased to reduce mismatch impact, then manufacturing precision improves, but power consumption increases
Solution Approach 1:
The patent uses parameter changes (adjustment signals modifying control node potentials) rather than increasing device size to correct mismatch. This approach corrects manufacturing variations by adjusting electrical parameters of existing transistors, avoiding the increased power consumption that would result from larger transistor sizes.
4Measurement precision
If offset adjuster transistors are selectively enabled to form composite transistors, then offset correction is achieved, but device complexity increases
Solution Approach 1:
The patent segments the correction function into two independent adjustment circuits: a first adjustment circuit for correcting offset errors and a second adjustment circuit for correcting gain errors. Each circuit independently adjusts one control node, dividing the complex mismatch correction problem into simpler, manageable segments that can be calibrated separately.
Solution Approach 2:
The patent implements preliminary calibration action by using calibration control circuits to determine optimal adjustment signals before normal operation. The first calibration circuit determines a first adjustment signal to correct offset, and the second calibration circuit determines a second adjustment signal to correct gain, preparing the comparator for accurate high-frequency operation before signals are applied.
Data Source
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AI summary
The present disclosure relates to the field of semiconductor circuit design, and in particular, to a comparator circuit, a method for correcting mismatch and a memory. The comparator circuit includes a first transistor, a second transistor, a load unit, a first adjustment circuit and a second adjustment circuit. A terminal of the first transistor is coupled to a first node, another terminal of the first transistor is coupled to a first control node, and a gate of the first transistor is configured to receive a first control signal. A terminal of the second transistor is coupled to the first node, another terminal of the second transistor is coupled to a second control node, and a gate of the second transistor is configured to receive a second control signal. A terminal of the load unit is coupled to a second node, and another terminal of the load unit is coupled to the first control node and the second control node. The first adjustment circuit is configured to adjust, according to a first adjustment signal, a node potential of the first control node after the first transistor becomes conductive based on the first control signal. The second adjustment circuit is configured to adjust, according to a second adjustment signal, a node potential of the second control node after the second transistor becomes conductive based on the second control signal. The mismatch between the two input transistors of the differential structure is thus eliminated, thereby improving the memory performance.