Comparator Circuit Mismatch Correction for High-Frequency Memory
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Solution Overview
Problem
High-frequency operating conditions in memory systems, such as LPDDR4 and LPDDR5, are significantly impacted by small mismatches between input transistors of a differential input structure, which cannot be effectively eliminated by traditional methods.
Innovation Solution
A comparator circuit is introduced, comprising a first and second transistor, a load circuit, and adjustment circuits. The circuit adjusts node potentials based on control signals to correct mismatches between the transistors, thereby improving memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional methods (such as increasing the size of the differential input transistors) are used to reduce mismatch, then manufacturing precision is improved, but device complexity and area increase
Solution Approach 1:
The patent changes the electrical parameters of the transistors by introducing adjustable gate voltages through the first and second adjustment circuits. By dynamically adjusting the gate voltages of the first and second transistors, the mismatch between them can be compensated without changing their physical dimensions or structure, thus resolving the contradiction between manufacturing precision and device complexity
Solution Approach 2:
The patent introduces adjustment circuits as intermediary components that mediate between the control signals and the transistors. These adjustment circuits generate corrected control signals that compensate for transistor mismatch, allowing precise control without directly modifying the transistor structures themselves
2Manufacturing precision
If transistor size is increased to reduce mismatch impact, then manufacturing precision is improved, but area of the device increases
Solution Approach 1:
Instead of increasing transistor size, the patent changes the electrical parameters (gate voltages) of the existing transistors through adjustment circuits. This allows mismatch compensation while maintaining the original transistor dimensions and circuit area
Solution Approach 2:
The patent transitions from spatial dimension (increasing transistor size) to electrical dimension (adjusting gate voltages) to address the mismatch problem. By operating in the electrical parameter space rather than physical dimension space, the solution achieves precision improvement without area increase
3Productivity
If differential input structure is used, then productivity is improved, but reliability deteriorates due to transistor mismatch at high frequencies
Solution Approach 1:
The patent implements a feedback mechanism where the adjustment circuits continuously monitor and correct the control signals based on the differential input signals. This feedback loop compensates for transistor mismatch effects, maintaining signal integrity even at high operating frequencies where mismatch would normally degrade reliability
Solution Approach 2:
The adjustment circuits serve as intermediary components between the differential input structure and the transistors, filtering and correcting the control signals to eliminate mismatch effects before they reach the transistors, thus protecting signal integrity while maintaining high-frequency operation
Data Source
AI summary
A comparator circuit includes a first transistor, a second transistor, a load circuit, a first adjustment circuit and a second adjustment circuit. A terminal of the first transistor is coupled to a first node, another terminal of the first transistor is coupled to a first control node, and a gate of the first transistor is configured to receive a first control signal. A terminal of the second transistor is coupled to the first node, another terminal of the second transistor is coupled to a second control node, and a gate of the second transistor is configured to receive a second control signal. A terminal of the load circuit is coupled to a second node, and another terminal of the load circuit is coupled to the first control node and the second control node.