Comparator-Based Modulo Circuits for Scalable Multipath Routing
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Solution Overview
Problem
Network devices face challenges in efficiently performing multipath routing due to the high cost and difficulty in scaling up modulo arithmetic circuits for integer division and remainder determination, which are resource-intensive and difficult to implement for larger group values.
Innovation Solution
Implementing multipath routing using multistage comparator-based modulo circuits that emulate integer division and remainder determination with combinational digital logic, reducing resource requirements and improving scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If modulo arithmetic circuits are used for multipath routing, then routing functionality is achieved, but circuit area and signal timing cost increase
Solution Approach 1:
The patent segments the modulo arithmetic operation into two separate functional blocks: an integer division circuit that computes the quotient, and a remainder determination circuit that computes the remainder. This segmentation allows each block to be optimized independently, reducing the overall circuit area while maintaining the required multipath routing functionality.
Solution Approach 2:
The patent introduces an intermediary quotient value as a mediator between the dividend (representative value) and the remainder (path identifier). By computing the quotient first and then using it to determine the remainder, the circuit avoids the complexity of direct modulo operation, thereby reducing circuit area and improving signal timing.
2Adaptability or versatility
If modulo arithmetic circuits are scaled up for higher group values, then more paths can be supported, but implementation difficulty and resource requirements increase
Solution Approach 1:
The patent segments the modulo operation into independent division and remainder blocks, which can be scaled by adjusting the bit-width of operands without increasing operational complexity. This allows the circuit to support higher group values (more paths) while maintaining manageable implementation difficulty.
Solution Approach 2:
The patent designs a universal modulo circuit structure that can handle different group values by simply changing the input operand width. The same circuit architecture serves multiple functions for different numbers of paths, reducing implementation complexity across various scaling scenarios.
3Ease of operation
If integer division and remainder determination are performed, then path selection is achieved, but signal timing and resource cost increase
Solution Approach 1:
The patent segments the path selection process into two sequential stages: integer division to compute the quotient, and remainder determination to select the path. This segmentation allows for optimized timing in each stage, reducing the overall signal timing cost compared to a monolithic modulo operation.
Solution Approach 2:
The patent performs the integer division operation first as a preliminary step, computing the quotient value that is then used in the remainder determination stage. This preliminary action optimizes the timing by preparing intermediate results that simplify the subsequent path selection operation.
Data Source
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AI summary
An example apparatus for a network device (100) is described. The apparatus can include: first logic configured to generate first codes for a packet, receive a second code that represents a number of paths through a network between the network device (100) and a destination of the packet; first circuits (402), coupled to the first logic, each configured to perform a comparison of one of the first codes with the second code and provide an output depending on the comparison; and a second circuit (602), coupled to the first logic and the first circuits (402), configured to select the output of one of the first circuits (402) as a third code that represents one of the paths.