Comparator Circuit With Observable Reference and Blind-Zone-Free Auto-Zero
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Solution Overview
Problem
Existing comparator circuits face issues with unobservable VREFH, gain errors due to capacitor mismatch, slower DAC transitions, lower input impedance, and periodic blind zones due to dedicated auto-zero phases, which affect precision and speed in high-bandwidth applications.
Innovation Solution
The proposed solution involves a comparator circuit with a matching capacitor and sampling capacitor configuration, using switching devices to manage phases for auto-zero and DAC operations, allowing for incremental offset voltage nullification and observable DAC references, eliminating blind zones and reducing capacitor mismatch errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dedicated auto-zero phase is used to nullify offset voltage, then offset voltage is contained, but periodic blind zones are created affecting productivity
Solution Approach 1:
The patent combines the auto-zero function with the normal comparison operation by using the same capacitor network for both purposes. The switching mechanism allows the capacitors to serve dual functions: storing offset voltage during comparison phases and performing auto-zero during dedicated phases, eliminating the need for separate blind zones.
Solution Approach 2:
The patent employs dynamic switching of capacitor connections through control signals that change the circuit topology in real-time. The capacitors are dynamically reconfigured between comparison mode and auto-zero mode, allowing continuous operation without periodic blind zones while maintaining offset voltage containment.
2Measurement precision
If sampling capacitor size is increased to contain gain error, then gain error is reduced, but DAC transition speed decreases affecting speed
Solution Approach 1:
The patent changes the effective capacitance value dynamically through switching mechanisms. Instead of using a large fixed capacitor, the system uses smaller capacitors that are switched in parallel when needed, providing large effective capacitance for gain error containment during comparison while maintaining small individual capacitor sizes for fast DAC transitions.
3Measurement precision
If capacitor mismatch is reduced to eliminate gain error, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent implements feedback through the auto-zero mechanism that measures and compensates for capacitor mismatch effects. The switching network allows the system to detect gain errors caused by capacitor mismatch and compensate for them by adjusting the reference voltage, thereby eliminating the need for extremely precise capacitor matching.
4Device complexity
If VREFH is made unobservable to simplify circuit, then device complexity is reduced, but reference observability is lost affecting measurement precision
Solution Approach 1:
The patent introduces an intermediary measurement mechanism that allows indirect observation of the reference voltage. Instead of directly accessing VREFH, the system uses the capacitor voltage relationships and comparison results to infer reference voltage status, maintaining reference observability while keeping the circuit simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster transient response, observable DAC references, and eliminates gain errors, ensuring precise and efficient signal comparison without periodic blind zones, suitable for safety-critical applications.
Implementation Method 1
capacitive digital-to-analog converter (CAP DAC) 120 connected to a node between sampling capacitor 111 and input terminal 122. As shown, CAPDAC 120 includes a capacitor (or capacitor array) 112 and array of switches 108-110
Implementation Method 2
comparator 102 connected to input terminals 121-122 (e.g., inverting and non-inverting terminals), which are capacitively coupled to matching capacitor 101 and sampling capacitor 111 of comparator circuit 100
Implementation Method 3
During auto-zero phase, switches 103, 104, 106, 107, 110 are closed and rest are open. During sampling phase, switches 103, 105, 110 are closed. During resolve phase, switches 106, 107 are closed
Data Source
AI summary
A comparator circuit includes a matching capacitor in series with a first switching device and a second switching device. The first and second switching devices are in parallel between the matching capacitor and a reference voltage. The comparator circuit further includes a sampling capacitor in series with a third switching device and a fourth switching device. The third switching device is in series between the sampling capacitor and a DAC, and the fourth switching device is in series between the sampling capacitor an input voltage. The comparator circuit further includes a comparator having an inverting input terminal and a non-inverting input terminal. The inverting input terminal is capacitively coupled to the matching capacitor and the non-inverting input terminal is capacitively coupled to the sampling capacitor. The comparator circuit further includes a fifth switching device and a sixth switching device in series between the matching capacitor and the sampling capacitor.