High-Speed Comparator Background Offset Calibration Without Bandwidth Loss
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Solution Overview
Problem
High-speed comparators in analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) face challenges due to offset voltage variations caused by random element mismatch, which conventional auto-zero techniques attempt to address by increasing preamplifier gain, but this reduces the tracking bandwidth.
Innovation Solution
A calibration system that includes an analog circuit, a switching circuit, state control logic, and an offset correction circuit, which alternates between a calibration phase and a comparison phase to disconnect the analog circuit from the preamplifier stage, apply a common mode reference, and adjust the decision latch's threshold voltage based on the history of states to reduce offset without increasing preamplifier gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional auto-zero techniques increase preamplifier gain to reduce comparator offset variation, then offset cancellation is improved, but tracking bandwidth is reduced
Solution Approach 1:
The patent segments the offset cancellation function into two independent parts: (1) preamplifier offset cancellation through auto-zero technique, and (2) latch offset cancellation through background calibration. This segmentation allows each part to be optimized independently, so the preamplifier gain can be kept moderate while still achieving overall offset cancellation through the additional latch calibration stage.
Solution Approach 2:
The patent performs latch offset calibration in advance during background operation, before the comparator is needed for signal comparison. The calibration phase measures and stores the latch offset value, which is then used to compensate for latch offset during normal operation. This preliminary action eliminates the need to increase preamplifier gain, preserving tracking bandwidth.
2Speed
If small device areas are employed in high-speed circuits, then speed is improved, but element mismatch increases causing offset voltage variations
Solution Approach 1:
The patent implements background calibration that operates automatically during normal converter operation, using the converter's own resources (power, signal paths) to perform self-calibration. The calibration circuit measures the actual latch offset and generates compensation values without requiring external calibration equipment or stopping normal operation, allowing high-speed circuits to maintain precision through continuous self-correction.
Solution Approach 2:
The patent establishes a feedback loop where the comparator's own output is used to detect offset errors, which are then fed back to adjust the decision threshold. The calibration circuit monitors the comparator output during calibration phases and uses this feedback information to generate appropriate offset compensation voltages, creating a closed-loop system that automatically corrects mismatch-induced offset variations.
Data Source
AI summary
A background offset calibration system for an analog signal comparator provides low offset without compromising tracking bandwidth. The comparator includes a preamplifier and a decision latch. A switching selectively couples outputs of an analog circuit to the inputs of the preamplifier stage. A state control logic alternatively operates the system in a first phase in which the analog circuit acquires an input signal while the comparator is calibrated, and a second phase in which a comparison is performed by the comparator. In the first phase, the switching circuit disconnects the outputs of the analog circuit from the preamplifier stage and applies a common mode reference to the inputs of the preamplifier. An offset correction circuit determines correction changes from a history of states of the decision latch across multiple sampling cycles. The offset correction circuit adjusts a threshold voltage of the decision latch by applying the correction changes.