Comparator Offset Calibration in High-Speed ADCs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed analog-to-digital converters (ADCs) face challenges in eliminating comparator offset voltage without assuming input signal statistics, leading to inefficiencies in power consumption and accuracy, especially in flash ADCs.
Innovation Solution
A comparison device with a delta-sigma modulation unit and compensation units that adjust threshold voltages of comparators based on differential codes from error patterns, canceling offset voltages without requiring invariant input signal statistics, and achieving robustness against process, voltage, and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the size of preamplifiers is enlarged to overcome threshold mismatch among comparators, then measurement precision is improved, but use of energy increases due to strong tradeoff among accuracy, speed, and power consumption
Solution Approach 1:
The invention extracts and eliminates the offset voltage component from comparator outputs through differential processing. By taking the difference between two comparator outputs that have undergone random chopping, the offset voltage (which is common to both) is canceled out, achieving threshold mismatch correction without enlarging preamplifier size.
Solution Approach 2:
The invention employs random chopping that periodically switches comparator inputs between normal and inverted states. This periodic action allows offset voltage to be separated from the actual signal through statistical processing, enabling offset elimination without increasing preamplifier dimensions.
2Device complexity
If background digital calibration is used to eliminate offset voltage, then device complexity is reduced, but productivity decreases due to slow settling behavior from statistics-based calibration
Solution Approach 1:
The invention performs offset calibration continuously in the background without requiring a separate calibration phase. The random chopping and differential processing operate concurrently with normal ADC conversion, eliminating offset voltage immediately rather than requiring preliminary calibration before operation.
Solution Approach 2:
The calibration process continues continuously during normal operation rather than being a discrete preliminary step. The random chopping and differential offset elimination operate throughout the ADC's working period, providing continuous correction without interrupting productivity.
3Ease of operation
If statistics-based calibration is employed to estimate offset voltage, then ease of operation is improved, but loss of time increases due to slow settling behavior
Solution Approach 1:
Random chopping periodically inverts comparator inputs, creating a time-varying signal where offset voltage appears as a DC component. This periodic action enables straightforward statistical extraction of offset through simple averaging, making operation easy while achieving fast convergence.
Solution Approach 2:
The invention uses feedback through continuous monitoring of comparator outputs and real-time differential processing. The offset correction is continuously updated based on ongoing measurements, providing easy operation with rapid settling through adaptive feedback rather than slow open-loop statistics.
Data Source
AI summary
The comparison device includes a first through second comparators, a chop switching unit, a delta-sigma modulation unit, and a first through second compensation units. The chop switching unit transmits a first and a second signals to two input terminals of the first comparator during a first period, and inverses the first and second signals during a second period. The delta-sigma modulation unit compares the comparison results of two parallel comparators and generates the digital control codes for the comparators with the awareness of the chop switching unit. The first and the second compensation units adjust the threshold voltages of the comparators according to the digital control codes and a step size for calibrating the offset voltages of two comparators. The calibration scheme requiring no assumption on the input signal statistics is background thus the comparison device will not interrupt normal operation and is immune to PVT variations.