Differential Comparator Offset Tuning Without Saturation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional offset comparators face limitations in offset range due to bias conditions, leading to saturation issues when voltage differences exceed certain values, affecting comparison accuracy.
Innovation Solution
A comparator circuit comprising a differential pair and current control circuit, where the current control circuit provides unequal current drawing abilities for the transistors, allowing for adjustable internal offset voltage and preventing saturation by using a degeneration resistor and tail transistors with varying sizes and impedances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional offset comparator is used, then comparison function is provided, but offset range is limited due to bias condition and saturation occurs when voltage difference exceeds certain value
Solution Approach 1:
The patent applies dynamics by making the current drawing ability of the differential pair transistors adjustable through a current control circuit. The transistors are configured with different current drawing abilities that can be dynamically controlled, allowing the offset voltage to be adjusted beyond conventional limits without entering saturation condition, thus expanding the offset range while maintaining comparison accuracy.
Solution Approach 2:
The patent changes the parameter of current drawing ability for the differential pair transistors through the current control circuit. By adjusting the current drawing abilities of the first and second transistors differently, the internal offset voltage can be varied to extend the offset range. This parameter change allows the comparator to operate accurately across a wider voltage difference range without saturation.
2Adaptability or versatility
If current control circuit provides unequal current drawing abilities, then offset tuning range is enhanced, but device complexity increases
Solution Approach 1:
The patent merges the current control function directly into the differential pair structure by configuring the first and second transistors with different current drawing abilities through shared current control circuitry. This integration approach enhances the offset tuning range while minimizing the increase in device complexity by combining multiple functions within the existing transistor framework.
3Object-affected harmful factors
If degeneration resistor and tail transistors with varying sizes are used, then kick-back noise is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by introducing degeneration resistors and tail transistors with specifically varied sizes at particular locations within the differential pair circuit. These localized modifications target the reduction of kick-back noise at the source while maintaining overall circuit functionality. The specific placement and sizing of these components address the noise issue without requiring extreme manufacturing precision across the entire circuit.
Data Source
AI summary
A comparator has a differential pair circuit, a current control circuit, and a latch. The differential pair circuit has first and second comparator transistors, and is arranged to compare a first input and a second input according to a clock signal to generate a result indicating whether a difference of the first and second inputs exceeds an internal offset. The current control circuit is coupled in series with the differential pair circuit, and configured to provide unequal abilities of drawing currents for the first and second comparator transistors.