Comparator Circuit With Parallel Auto-Zero for Faster AD Conversion
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Solution Overview
Problem
In solid-state imaging devices, the existing AD conversion processing speed is limited due to the need for automatic zero operation twice within the AD conversion circuit, particularly in comparator configurations like those described in Japanese Unexamined Patent Application Publication No. 2011-229120, which complicates the operation and increases power consumption and device size.
Innovation Solution
A comparator design featuring a differential pair of transistors with additional transistors that connect to power source voltages and drain electrodes, allowing for parallel auto-zero operation of the amplifying units, thereby eliminating the need for external voltage adjustments and simplifying the circuit configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the existing comparator configuration is used with sequential auto-zero operation, then the circuit operation is simplified, but the AD conversion processing speed is limited and power consumption increases
Solution Approach 1:
The comparator circuit is divided into two separate amplifying units (first and second amplifying units), each capable of independent auto-zero operation. This segmentation allows parallel processing of different signal phases without interfering with each other, thereby increasing the overall AD conversion speed while maintaining manageable circuit complexity through modular design.
Solution Approach 2:
The patent combines the auto-zero operations of both amplifying units to occur simultaneously in parallel, rather than sequentially. By merging the timing of these operations, the circuit achieves faster overall processing speed without proportionally increasing power consumption, as both units operate concurrently during the auto-zero phase.
2Adaptability or versatility
If external voltage adjustments are implemented for comparator operation, then the comparator can operate in accordance with signal levels, but device size and power consumption increase
Solution Approach 1:
Each amplifying unit is equipped with its own dedicated auto-zero circuitry and transistor configuration, allowing it to automatically adjust and calibrate itself without requiring external voltage adjustments. This self-service capability maintains the comparator's adaptability to different signal levels while eliminating the power consumption associated with external adjustment mechanisms.
3Adaptability or versatility
If external voltage adjustments are implemented for comparator operation, then the comparator can operate in accordance with signal levels, but device size increases
Solution Approach 1:
The auto-zero functionality is merged directly into the internal structure of each amplifying unit, combining the calibration function with the signal amplification function. This integration eliminates the need for separate external adjustment circuits, thereby maintaining adaptability while reducing the overall device size.
Solution Approach 2:
Each amplifying unit is designed to perform multiple functions: signal amplification, auto-zero calibration, and adaptation to different signal levels. This multi-functionality is achieved through the transistor configuration that allows the same circuit elements to serve both amplification and calibration purposes, reducing the need for additional dedicated components and thereby minimizing device size.
Data Source
AI summary
A comparator includes: a first amplifying unit that includes a differential pair configured with a pair of transistors which are first and second transistors, and amplifies a difference of signals input to each of the gate electrodes of the first and second transistors, to output; a second amplifying unit that amplifies the signal output from the first amplifying unit; a third transistor that connects the first transistor to a power source voltage; a fourth transistor that connects the second transistor to the power source voltage; a fifth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the third transistor; and a sixth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the fourth transistor.