Comparator Output Stage With Pre-Charging and Early Reset
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Solution Overview
Problem
Existing comparator circuits face a trade-off between speed and noise, with increased current for speed leading to higher noise and power consumption, and reduced current for noise reduction resulting in slower regeneration phases. Additionally, the reset phase must balance speed and hysteresis performance, often requiring large transistors that increase parasitic capacitance and noise.
Innovation Solution
A comparator circuit with a pre-charging phase using a small current to reduce noise, followed by a rapid increase in current for the regeneration phase, and an early reset output stage that feeds forward to reduce hysteresis without increasing reset time or internal capacitance, utilizing two-phase enable clock signals and PMOS and NMOS transistors to manage signal amplification and short-circuiting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If current is increased to improve speed, then regeneration phase speed is improved, but noise increases
Solution Approach 1:
The patent divides the operation into distinct phases: pre-amplification phase with smaller current to reduce noise, and regeneration phase with larger current to ensure speed. This temporal segmentation allows optimization of current for each phase independently, resolving the contradiction between speed and noise.
Solution Approach 2:
The pre-charging phase performs preliminary signal amplification before the main regeneration phase. By preparing the signal in advance with controlled current, the subsequent regeneration can proceed faster with higher current without excessive noise penalty, as the signal is already partially amplified.
2Object-generated harmful factors
If current is reduced to decrease noise, then noise is reduced, but regeneration phase speed decreases
Solution Approach 1:
The patent segments the operation into pre-amplification (lower current) and regeneration (higher current) phases. This allows the system to spend more time at lower current for noise reduction while maintaining overall speed through the structured two-phase approach.
Solution Approach 2:
The pre-charging phase continuously prepares the signal during the first half of the clock cycle, ensuring that when the regeneration phase begins, the signal is already amplified and ready for rapid conversion, maintaining continuous useful action without interruption.
3Reliability
If reset time is extended to clear all internal nodes, then hysteresis performance is improved, but comparator cycle time increases
Solution Approach 1:
The output stage is reset in advance during the pre-charging phase, before the main comparison and regeneration phases complete. This preliminary reset action ensures that the output is cleared early, allowing the comparator to be ready for the next cycle without waiting for all internal nodes to settle.
Solution Approach 2:
The patent uses dynamic control of reset timing based on clock phases. The reset is activated during specific phases (pre-charging and after regeneration) rather than continuously, optimizing the balance between clearing internal nodes and maintaining hysteresis performance while minimizing cycle time.
4Speed
If large MOS transistor is used for fast clearing, then reset speed is improved, but parasitic capacitance and initial noise increase
Solution Approach 1:
The patent applies different transistor sizes to different parts of the circuit based on local requirements. Larger transistors are used where fast switching is critical (output stage reset), while smaller transistors are used in signal paths where noise and parasitic capacitance would be problematic. This localized optimization resolves the contradiction.
Data Source
AI summary
A comparator circuit has a pre-charging and early reset output stage. The comparator circuit includes: a first pre-charging transistor and a second pre-charging transistor. A gate of the first pre-charging transistor is connected to a pre-charging signal, and a gate of the second pre-charging transistor is connected to a main clock signal, wherein the pre-charging signal is enabled earlier than the main clock signal. At a pre-charging phase, there is a small electric current, and a comparator slowly amplifies an input small signal to reduce noise; and the electric current is increased after a certain time delay, such that on the basis of pre-charging, the comparator rapidly completes a pre-amplification phase and then enters a regeneration phase.