Comparator Output Circuit Precharge for Low-Jitter Single-Slope ADCs
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Solution Overview
Problem
In image sensors, the increasing resolution and power consumption demands lead to space constraints for comparators in analog to digital converters, causing noise and output jitter issues due to current spikes and capacitance challenges in the comparator's output circuitry.
Innovation Solution
The implementation of a comparator output circuitry with a second and third stage, where the second stage current source is removed and the output is pre-charged to ground prior to conversion, and the inclusion of a diode or feedback stages to enhance power supply rejection ratio and reduce noise, thereby minimizing current variation and area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the comparator size is reduced to meet space constraints in high-resolution image sensors, then area consumption is reduced, but noise and output jitter increase due to current spikes and capacitance challenges
Solution Approach 1:
The comparator output circuitry is divided into multiple stages (first stage, second stage, third stage) with distinct functions. The first stage performs the actual comparison, the second stage handles current source operations, and the third stage provides final output. This segmentation allows each stage to be optimized independently, reducing overall noise while maintaining compact area.
Solution Approach 2:
The output of the second stage is pre-charged to ground prior to conversion through a reset signal. This preliminary action prepares the circuit in a known state, eliminating residual charges that would cause noise and jitter during the actual conversion process, thereby improving output stability in the reduced-area comparator.
2Area of moving object
If the comparator area is minimized for high-resolution sensors, then integration density increases, but power supply rejection ratio deteriorates due to current variation
Solution Approach 1:
A feedback mechanism is implemented where the output of the third stage is fed back to the input of the second stage. This feedback loop compensates for current variations and power supply fluctuations, maintaining a stable operating point and improving power supply rejection ratio even in the minimized comparator structure.
Solution Approach 2:
The patent optimizes the capacitance values and current source parameters in the second stage to minimize current variation. By carefully selecting and adjusting these parameters, the comparator achieves better power supply rejection while maintaining the reduced area required for high-resolution image sensor integration.
3Productivity
If the comparator is made compact for column level ADCs, then productivity and integration increase, but output circuitry noise increases due to current spikes
Solution Approach 1:
The reset signal is applied periodically to pre-charge the second stage output to ground before each conversion cycle. This periodic action ensures that current spikes are controlled and synchronized, preventing random noise generation while maintaining the compact comparator design needed for high-productivity column level ADCs.
Solution Approach 2:
The third stage acts as an intermediary between the second stage current source and the final output. It buffers and conditions the signal, filtering out current spikes and noise generated in the second stage before the signal is used for digital conversion, thereby reducing harmful effects while maintaining integration efficiency.
Data Source
AI summary
An output circuit for use with a comparator includes a first transistor having a control terminal coupled to receive an output signal from a first stage of the comparator. A second transistor is coupled between the first transistor and a reference voltage. The second transistor has a control terminal coupled to receive a first reset signal. The second transistor is coupled to precharge a first output node of the first transistor between the first and second transistors to the reference voltage prior to a comparison operation of the comparator. An output stage has an input node coupled to the first output node. The output stage is coupled to generate an output voltage of the output circuit at an output node of the output stage in response to the first output node.