Comparator Pre-Charging Circuit for Faster SAR-ADC Decisions

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Solution Overview

Problem

High-speed comparators are necessary for successive approximation register analog-to-digital converters (SAR-ADC) to effectively compare voltage levels, but existing solutions do not efficiently manage current flow, leading to suboptimal operating speeds.

Innovation Solution

A comparing device with a comparing circuit, a first current generating circuit, and a second current generating circuit, where the second current generating circuit continuously provides a smaller current to a common node, pre-charging it to a specific voltage level when the comparing circuit is disabled, allowing for faster comparison when re-enabled.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If existing comparator solutions are used without pre-charging current management, then the device complexity is lower, but the operating speed and decision time are suboptimal

Engineering Contradiction:
Improveoperating speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by continuously pre-charging the common node to a specific voltage level (e.g., half of the reference voltage) before a comparison operation is needed. This pre-charging is performed by a second current generating circuit that operates continuously or periodically to maintain the common node at an optimal starting voltage, thereby reducing the decision time when the comparator is re-enabled.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamics by switching between two current generating circuits based on operational needs. The first current generating circuit provides a larger current during active comparison to quickly charge/discharge the common node, while the second current generating circuit provides a smaller continuous current to maintain the pre-charged state when the comparator is disabled, optimizing performance across different operational phases.

Inventive Principle:
Principle #15Dynamics

2Loss of time

If a larger current is used during comparison, then the decision time is reduced, but the power consumption increases

Engineering Contradiction:
Improvedecision timeVSAvoidpower consumption
Core Design Contradiction:
Loss of timeVSUse of energy by moving object

Solution Approach 1:

The patent applies periodic action by using the second current generating circuit to continuously or periodically maintain the pre-charged state of the common node, rather than continuously applying large current. The first current generating circuit is activated only during active comparison periods, providing large current temporarily to complete the comparison quickly, while the second circuit handles the baseline maintenance with smaller current consumption.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent implements parameter changes by dynamically adjusting the current magnitude based on operational phase. During active comparison, the first current generating circuit provides a larger current (higher parameter value) to reduce decision time. When the comparator is disabled, the second current generating circuit provides a smaller current (lower parameter value) to maintain the pre-charged state, thereby reducing overall power consumption while preserving speed performance when needed.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11811408B2Comparing device and method of controlling comparing device
Publication Date: 2023.11.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11811408B2 patent drawing
  • US11811408B2 patent drawing
  • US11811408B2 patent drawing

AI summary

A method includes: selectively generating a first current by a first current generating circuit according to a first control signal; generating a second current by a second current generating circuit; and comparing a first input signal and a second input signal at a common node to generate an output signal according to the first current, the second current, and a second control signal. The second control signal and the first control signal are in-phase with each other.