Top-Plate Sampled Comparator Pre-Conditioning for SAR ADC Linearity
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Solution Overview
Problem
Medium- to high-resolution SAR ADCs face issues with total harmonic distortion due to the non-linear gate capacitance of transistors used in top-plate sampling systems, which affect sampling linearity.
Innovation Solution
A method is introduced to maintain a constant voltage across non-linear capacitors during the sampling phase of the comparator, using sampling transistors, switches, and circuitry to pre-condition the comparator, ensuring linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the input is sampled onto the gate of a transistor using gate capacitance as the sampling capacitor, then the sampling system can be implemented in a compact integrated circuit manner, but the non-linear gate capacitance results in total harmonic distortion and poor sampling linearity
Solution Approach 1:
The patent applies preliminary action by pre-charging the sampling transistor gates to a predetermined voltage level before the actual sampling operation. This pre-conditioning ensures that during the sampling phase, the transistors operate in a linear region where the gate capacitance characteristics are more linear, thereby reducing harmonic distortion while maintaining the compact integrated circuit implementation
Solution Approach 2:
The patent changes the operating parameters of the sampling transistors by dynamically adjusting their gate voltages. During sampling, the gates are held at a constant predetermined voltage to linearize the capacitance characteristics. This parameter change transforms the transistor operation from non-linear to more linear, resolving the contradiction between compact implementation and sampling linearity
2Measurement precision
If medium- to high-resolution SAR ADCs use top-plate sampling systems, then the ADC can achieve higher resolution, but the non-linear gate capacitance causes total harmonic distortion that degrades performance
Solution Approach 1:
The patent applies preliminary action by pre-charging the sampling transistor gates to a predetermined voltage level before the actual sampling operation. This pre-conditioning ensures that during the sampling phase, the transistors operate in a linear region where the gate capacitance characteristics are more linear, thereby reducing harmonic distortion while maintaining the compact integrated circuit implementation
Solution Approach 2:
The patent changes the operating parameters of the sampling transistors by dynamically adjusting their gate voltages. During sampling, the gates are held at a constant predetermined voltage to linearize the capacitance characteristics. This parameter change transforms the transistor operation from non-linear to more linear, resolving the contradiction between compact implementation and sampling linearity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains sampling linearity in top-plate sampled comparators, improving performance in medium- to high-resolution ADCs.
Implementation Method 1
maintaining a constant voltage across non-linear capacitors of the comparator during a sampling phase of the comparator
Data Source
AI summary
A successive approximation register analog-to-digital converter may include a reference digital-to-analog converter, a successive approximation register, and a top-plate sampled comparator configured to compare a reference signal generated by the reference digital-to-analog converter to an analog input signal in order to generate a comparator output to the successive approximation register. The top-plate sampled comparator may include sampling transistors, sampling switches, non-linear capacitors, and circuitry configured to pre-condition the comparator by maintaining a constant voltage across non-linear capacitors of the top-plate sampled comparator during a sampling phase of the comparator in order to maintain sampling linearity of the top-plate sampled comparator.