Comparator Reference Alignment for Memory Interface Skew
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Solution Overview
Problem
Signal skew occurs in memory interfaces due to the mismatch between fully differential clock/strobe pads and pseudo differential data receiver pads, leading to performance compromise and common mode errors.
Innovation Solution
A system comprising an extraction module to extract the AC component of input signals and a superimposing module to superimpose it on a common reference voltage, ensuring all signals are at the same level, thereby reducing skew through a comparator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the same differential comparator is used for both clock pads and data receiver pads, then device complexity is reduced, but signal skew increases due to mismatched characteristics between fully differential clock pads and pseudo differential data receiver pads
Solution Approach 1:
The patent applies local quality by making the clock pad receiver and data receiver pads use different comparator configurations tailored to their specific signal types. Clock pads use a differential comparator optimized for fully differential signals, while data receiver pads use a pseudo differential comparator optimized for pseudo differential signals. This localized optimization resolves the signal skew issue without requiring a single universal comparator design.
Solution Approach 2:
The patent changes key parameters of the comparator circuits to match the characteristics of different pad types. Specifically, the clock pad comparator is designed with parameters optimized for fully differential signals, while the data receiver comparator is designed with parameters optimized for pseudo differential signals. This parameter differentiation eliminates signal skew while maintaining overall system reliability.
2Adaptability or versatility
If fully differential clock/strobe pads and pseudo differential data receiver pads are used, then signal characteristics are optimized for their respective functions, but signal skew occurs due to non-equivalent mean voltage levels
Solution Approach 1:
The patent introduces intermediary voltage level adjustment circuits that mediate between the fully differential clock signals and pseudo differential data signals. These intermediary circuits convert and align the voltage levels of different signal types to a common reference, enabling accurate comparison without signal skew while preserving the advantages of both signal types.
Solution Approach 2:
The patent achieves equipotentiality by designing the comparator reference voltages and bias circuits to establish a common voltage baseline for both clock and data receivers. This ensures that despite the different differential configurations, both receiver types operate from the same voltage reference level, eliminating common mode errors and signal skew.
Data Source
AI summary
Skew is reduced by extracting the AC component of an input signal and superimposing it on a common reference voltage to produce a resulting voltage. The resulting voltage is provided as an input to a comparator, which compares it to the reference voltage to provide a final output. Thus, all signals fed to a system, in accordance with an embodiment, are referenced at the same DC level and hence, skew is reduced.