Comparator-Reuse Sorting Circuit for Low-Area Median Filtering
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Solution Overview
Problem
Hardware implementations of median filters require a large number of comparators, leading to significant die area requirements and excessive power consumption, making them unfeasible for certain applications, especially when processing large amounts of data at high rates.
Innovation Solution
A sorting circuit that re-uses a single stage of comparators over multiple phases using multiplexors and a scheduling circuit to reduce the number of comparators and registers, achieving a linear increase in hardware requirements with input sequence values, rather than the conventional exponential increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sorting network based on multiple stages of comparators is used to implement median filtering, then the filtering performance is improved, but the die area and power consumption increase significantly
Solution Approach 1:
Multiple comparator stages are merged into a single comparator stage by time-multiplexing the same physical comparator across different phases of the sorting algorithm. The scheduling circuit coordinates the reuse of the single comparator through multiple phases, allowing one comparator to perform the work of what would traditionally require multiple comparators, thereby reducing die area while maintaining sorting capability
Solution Approach 2:
The system transitions from a static multi-comparator architecture to a dynamic single-comparator architecture that changes its configuration over time. The scheduling circuit dynamically assigns different comparison tasks to the single comparator across different phases, and multiplexors dynamically route different data pairs to the comparator inputs, enabling the same hardware to adaptively perform multiple comparison functions sequentially
2Productivity
If multiple stages of comparators are used for sorting, then the sorting capability is improved, but the number of comparators increases exponentially with input window size
Solution Approach 1:
The sorting process is divided into periodic phases where a single comparator is reused in a cyclic manner across different phases. The scheduling circuit implements this periodic action by systematically assigning comparison tasks to the single comparator in different phases, allowing the same hardware element to serve multiple sorting functions over time rather than requiring dedicated comparators for each function
Solution Approach 2:
A single comparator is designed to be universal and perform multiple comparison functions that would traditionally require multiple specialized comparators. Through the coordination of the scheduling circuit and the routing of multiplexors, one comparator becomes multi-functional, capable of comparing different data pairs across different phases, thereby reducing the total number of comparators needed from exponential to linear scaling with input size
3Speed
If a large number of comparators are implemented in hardware, then the sorting speed is improved, but the power consumption becomes excessive
Solution Approach 1:
Multiple comparator operations are merged into a single physical comparator by executing comparisons sequentially across different phases. The scheduling circuit ensures that the single comparator is efficiently utilized across multiple phases to complete the sorting task, reducing the number of active comparator circuits from many to one, thereby significantly reducing power consumption while maintaining sorting throughput through phased execution
Data Source
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AI summary
Techniques are provided for sorting input data values using a sorting circuit. The sorting circuit includes a single stage of comparators coupled to a bank of registers. Multiplexors and a sequencer are used to route the comparator outputs back to the comparator inputs such that the comparators may be re-used over multiple sorting phases so as to order an input sequence of data values into a partially-sorted sequence or into a completely-sorted sequence that is monotonically increasing or decreasing. By re-using the comparators, the hardware required for such sorting is significantly reduced relative to conventional techniques. Also described are techniques for median filtering, which use a sorted sequence as output by the sorting circuit described herein.