Ultra-low Power Comparator With Sampling Control Loop
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Solution Overview
Problem
Comparators in power converters consume continuous quiescent current even when not actively comparing, which reduces battery life and increases power consumption, and existing techniques fail to balance minimizing this current with maintaining adequate bandwidth and voltage accuracy.
Innovation Solution
A dynamic adjustment of the sampling clock frequency and aperture window based on load conditions, using a clock controller that enables the comparator only when necessary, thereby reducing quiescent current while maintaining acceptable voltage error.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the comparator is continuously powered to maintain adequate bandwidth and voltage accuracy, then the voltage control accuracy is improved, but the quiescent current consumption increases
Solution Approach 1:
The comparator is powered periodically rather than continuously. A controller selectively enables the comparator based on whether a voltage comparison is needed, turning it off during idle periods to eliminate quiescent current consumption while maintaining voltage control accuracy when comparisons are performed.
Solution Approach 2:
The comparator's power state is dynamically adjusted based on operational requirements. The controller monitors system conditions and adaptively switches the comparator between enabled and disabled states, optimizing the balance between voltage control accuracy and power consumption in real-time.
2Speed
If the comparator sampling frequency is increased to maintain adequate bandwidth, then the bandwidth is improved, but the quiescent current consumption increases
Solution Approach 1:
The comparator operates at high sampling frequency only periodically when voltage comparisons are required, rather than continuously. The controller manages the timing to ensure adequate bandwidth for comparisons while allowing the comparator to remain dormant during idle periods, thereby reducing overall power consumption.
3Use of energy by moving object
If the comparator is disabled to reduce quiescent current, then the power consumption is reduced, but the voltage control response time increases
Solution Approach 1:
The controller proactively determines when voltage comparisons are needed and enables the comparator in advance of actual comparison operations. This preliminary action ensures the comparator is ready to operate immediately when required, maintaining fast response time while allowing it to remain disabled during extended idle periods to reduce power consumption.
Solution Approach 2:
The comparator's operational state is dynamically controlled based on real-time system needs. The controller monitors voltage conditions and adaptively switches the comparator between enabled and disabled states, ensuring fast response when voltage control is needed while minimizing power consumption during idle periods.
Data Source
AI summary
Methods and apparatus for minimizing average quiescent current for a desire voltage error in a comparator are disclosed. An example method includes receiving a first voltage and a reference voltage, outputting a second voltage when the first voltage is lower than the reference voltage, wherein the outputting of the second voltage increases the first voltage, counting a number of clock cycles while the first voltage is higher than the reference voltage, comparing the number of clock cycles to a maximum number of clock cycles and a minimum number of clock cycles, when the number of clock cycles is above the maximum number of clock cycles, decreasing a frequency of a clock associated with the number of clock cycles, and when the number of clock cycles is below the minimum number of clock cycles increase the frequency of the clock.