Comparator Test Point Circuit for Hard-to-Detect Fault Coverage
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Solution Overview
Problem
Testing comparator circuits is challenging due to complex logic that makes controlling and observing faults difficult, leading to incomplete test coverage and increased defective device risk.
Innovation Solution
A custom NOR-based test point circuit with an inverted input is used to provide controllability and observability, allowing for the testing of faults like stuck-at-one faults in comparator circuits, and can be implemented using a reused storage circuit to reduce space constraints and improve power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional test circuit is used for comparator circuits, then the device complexity is reduced, but the test coverage is insufficient and fault detection capability is limited
Solution Approach 1:
A test point circuit is introduced as an intermediary component between the comparator circuit and the test equipment. This test point circuit includes logic gates (such as NOR gates with inverted inputs) that mediate the testing process, enabling detection of stuck-at-one faults and other defects that would otherwise be undetectable with conventional direct testing methods.
2Reliability
If the comparator circuit is fully tested with comprehensive test patterns, then the test coverage is improved, but the testing time and cost increase
Solution Approach 1:
The test point circuit extracts and isolates specific fault conditions (such as stuck-at-one faults on clock-enable signals) from the complex comparator circuit logic. By separating these critical test points, the testing process can focus on specific fault modes rather than requiring exhaustive testing of all possible fault conditions, thereby reducing test pattern count and testing time while maintaining high test coverage.
3Reliability
If additional test circuits are added to improve fault detection, then the test coverage is improved, but the space constraints are violated
Solution Approach 1:
The test point circuit is designed to be multi-functional, serving both as a normal circuit component during operation and as a test observation point during testing. The same logic gates and interconnections that perform the comparator function also serve as the test point circuit, eliminating the need for separate dedicated test circuitry and thus avoiding additional area overhead while still providing enhanced fault detection capability.
Data Source
AI summary
Techniques and apparatuses are described for testing a comparator circuit. In example aspects, a test point circuit can provide controllability and observability of signals and faults in a comparator circuit. The test point circuit uses a custom NOR-based design with an inverted input. With this custom design, the test point circuit can test for faults that other designs are unable to support. Example faults include stuck-at-one faults at an input of the comparator circuit or on a clock-enable signal. The use of the test point circuit improves test coverage and reduces test pattern count, which reduces the time and cost of testing a comparator circuit. In certain aspects, a storage circuit can be reused to implement the test point circuit, which enables testing of a comparator circuit to be implemented within space-constrained devices.