CMOS Image Sensor Comparator Topology for Power-Fluctuation ADC Errors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In analog-to-digital converters (ADCs), particularly in solid-state imaging devices, there is a trade-off between noise reduction and inversion delay, and when multiple ADCs operate simultaneously, power fluctuations introduce errors in AD conversion results.
Innovation Solution
A comparator configuration with a first amplifier, a second amplifier, and a second transistor of the same polarity, where the gate of the second transistor is connected to the output node of the first amplifier, and the source and drain are connected to a fixed potential, allowing for controlled capacitance changes to manage noise and inversion delay, and incorporating a PMOS or NMOS transistor to mitigate power fluctuation noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the capacitance value of the band-limiting capacitor is increased to reduce noise, then noise is reduced, but inversion delay increases
Solution Approach 1:
The patent applies the dynamics principle by making the capacitance value of the band-limiting capacitor variable rather than fixed. The capacitance is dynamically adjusted based on the operating conditions: a first capacitance value is used when the reference signal is tilted to minimize inversion delay, while a second capacitance value is used when the reference signal is not tilted to reduce noise. This dynamic adaptation resolves the contradiction between noise reduction and inversion delay by optimizing the capacitance value for each specific operating state.
Solution Approach 2:
The patent implements parameter changes by modifying the capacitance value of the band-limiting capacitor based on the state of the reference signal. The control circuit detects whether the reference signal is tilted and accordingly selects different capacitance values. This parameter adjustment allows the system to achieve both low noise (when capacitance is increased) and low inversion delay (when capacitance is decreased), depending on the operational requirements.
2Productivity
If multiple ADCs operate simultaneously to increase productivity, then conversion throughput increases, but power fluctuations introduce errors in AD conversion results
Solution Approach 1:
The patent introduces a capacitance holding circuit as an intermediary element that stabilizes the reference potential during simultaneous ADC operations. This holding circuit maintains a stable reference voltage level even when multiple ADCs are converting signals at the same time, thereby preventing power fluctuations from affecting conversion accuracy. The intermediary circuit acts as a buffer between the power supply and the ADC reference inputs, isolating the conversion process from power variations.
Solution Approach 2:
The patent applies beforehand cushioning by pre-stabilizing the reference potential using the capacitance holding circuit before simultaneous ADC conversions begin. The holding circuit is designed to maintain stable reference voltages in advance, cushioning against the inevitable power fluctuations that occur during parallel operations. This preparatory stabilization ensures that even when multiple ADCs operate simultaneously, the reference potentials remain stable and conversion errors are minimized.
Data Source
AI summary
The present technology relates to a solid-state imaging device, an electronic apparatus, and an AD converter that are capable of suppressing the occurrence of an error in AD conversion results.The solid-state imaging device includes a pixel section having a plurality of pixels, a comparator for comparing a pixel signal outputted from the pixels with a reference signal, and a counter for counting the time of comparison made by the comparator. The comparator includes a first amplifier for comparing the pixel signal with the reference signal, a second amplifier that has a first transistor and amplifies an output signal of the first amplifier, and a second transistor having the same polarity as the first transistor. A gate of the second transistor is connected to an output end of the first amplifier, and a source and a drain of the second transistor are connected to the same fixed potential as a source of the first transistor. The present technology is applicable, for example, to a CMOS image sensor.