Comparator Trigger Timing Control for Wide Input and Low Noise
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Solution Overview
Problem
Existing comparators, such as two-stage and single-stage comparators, suffer from higher offset variation and worse noise performance due to input voltage levels near the supply voltage, making them unsuitable for wide input voltage ranges commonly found in power management integrated circuits (PMICs).
Innovation Solution
A multi-stage or single-stage comparator design incorporating a control circuit to manage the start time of subsequent stages, optionally with gain boosting, ensuring optimal operation across a wide input range by triggering these stages at the moment of maximum gain of the preceding stage, thereby minimizing noise and offset contributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a typical two-stage comparator is used, then the comparator can operate at high input voltage levels near the supply voltage, but the offset and noise performance deteriorate because the second stage does not trigger at the optimal moment
Solution Approach 1:
The patent applies dynamic control by making the trigger timing of the second stage adaptable to the input voltage level. The control circuit dynamically adjusts when the second stage triggers based on the instantaneous state of the first stage output, ensuring optimal operation across the entire input voltage range rather than being fixed for a specific operating point.
Solution Approach 2:
The patent changes the timing parameter of the second stage trigger based on the input voltage level. By monitoring the first stage output and triggering the second stage at different moments depending on the voltage level, the system optimizes the gain and noise performance for each operating condition.
2Adaptability or versatility
If a typical single-stage comparator is used, then the comparator can handle wide input voltage ranges, but the noise performance worsens because the second sub-stage triggers when the first sub-stage gain has already reduced
Solution Approach 1:
The patent implements dynamic trigger timing control where the second sub-stage is triggered at different moments based on the input voltage level and the instantaneous gain of the first sub-stage. This dynamic adjustment ensures that the second sub-stage always starts when the signal-to-noise ratio is optimal, preventing noise degradation across the full input voltage range.
Solution Approach 2:
The control circuit uses feedback from the first sub-stage output to determine the optimal trigger moment for the second sub-stage. By monitoring the gain and output level of the first sub-stage, the system feedback-controls when to activate the second sub-stage, ensuring noise performance is maintained across varying input conditions.
3Object-generated harmful factors
If the second stage triggers early to capture maximum gain from the first stage, then noise performance improves, but offset increases because the first stage has not settled
Solution Approach 1:
The patent applies dynamic timing adjustment where the trigger moment of the second stage is not fixed but adapts to the settling behavior of the first stage. By dynamically determining when the first stage output has settled sufficiently while still capturing the gain peak, the system balances both noise and offset performance.
Solution Approach 2:
The control circuit performs preliminary monitoring of the first stage output to detect when settling is complete and when maximum gain is available. This preliminary action allows the system to trigger the second stage at the optimal moment that satisfies both noise and offset requirements.
Data Source
AI summary
A multi-stage comparator includes a first stage circuit, a second stage circuit, and a control circuit. The first stage circuit receives an input signal of the multi-stage comparator, generates a first-stage output signal according to the input signal, and outputs the first-stage output signal at an output port of the first stage circuit. The second stage circuit receives a second-stage input signal at an input port of the second stage circuit, and performs a second-stage operation to generate an output signal of the multi-stage comparator. The control circuit is coupled between the output port of the first stage circuit and the input port of the second stage circuit, and controls a start time of the second-stage operation.