Comparator Voltage Conversion for Fast Low-Power Pixel ADCs
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Solution Overview
Problem
In solid-state imaging apparatuses, there is a challenge in reducing power consumption while maintaining or enhancing the decision speed of comparators, particularly in scenarios where space is limited, such as within pixels, where traditional designs often compromise on either performance or efficiency.
Innovation Solution
A comparator design incorporating a differential input circuit operating at a first power source voltage, a positive feedback circuit operating at a lower second power source voltage, and a voltage converting circuit to speed up transition times, with the differential input circuit's source voltage set lower than 0 V, allowing for efficient signal conversion and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the comparator is designed with higher performance (faster decision speed), then the decision speed is improved, but power consumption increases
Solution Approach 1:
The comparator is divided into two functional segments: a differential input circuit operating at a higher first power source voltage for fast signal comparison, and a positive feedback circuit operating at a lower second power source voltage for controlled output stabilization. This segmentation allows each part to operate at optimal voltage levels, achieving fast decision speed while reducing overall power consumption.
Solution Approach 2:
Different voltage levels are applied to different parts of the comparator circuit. The differential input circuit receives the first power source voltage (higher) for rapid response, while the positive feedback circuit receives the second power source voltage (lower) for stable operation. This local quality differentiation optimizes both speed and power efficiency in their respective functional zones.
2Area of stationary object
If the comparator circuit area is reduced to fit within pixel constraints, then area efficiency is improved, but decision speed deteriorates
Solution Approach 1:
The comparator functionality is segmented between two voltage domains, allowing compact integration within the pixel while maintaining fast decision speed through the high-voltage differential input stage. The lower-voltage feedback stage provides stable operation without requiring additional area for buffering or level conversion circuits.
3Use of energy by moving object
If the power source voltage is reduced to lower power consumption, then power consumption is improved, but decision speed deteriorates
Solution Approach 1:
The circuit is segmented into two voltage domains: the differential input circuit operates at a higher first power source voltage to ensure fast decision speed, while the positive feedback circuit operates at a lower second power source voltage to reduce power consumption. This dual-voltage architecture resolves the trade-off by assigning different voltage levels to different functional requirements.
Solution Approach 2:
Different voltage qualities are applied locally to different circuit blocks based on their functional requirements. The high-voltage region provides speed-critical operations, while the low-voltage region handles power-sensitive operations, achieving both fast response and low power consumption simultaneously.
Data Source
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AI summary
The present disclosure relates to a comparator, an AD converter, a solid-state imaging apparatus, an electronic apparatus, and a method of controlling a comparator each of which enables power consumption to be reduced while a decision speed of the comparator is enhanced. A comparator, including: a differential input circuit operating at a first power source voltage, and outputting a signal when a voltage of an input signal is higher than a voltage of a reference signal; a positive feedback circuit operating at a second power source voltage lower than the first power source voltage, and speeding up a transition speed when a comparison result signal representing a result of comparison in voltage between the input signal and the reference signal is inverted on the basis of an output signal from the differential input circuit; and a voltage converting circuit converting the output signal from the differential input circuit into a signal corresponding to the second power source voltage, in which a source voltage of the differential input circuit is a voltage lower than 0 V. The present disclosure, for example, can be applied to an ADC or the like which is arranged for each pixel of a solid-state imaging apparatus.