Compare and Branch Mechanism for Flexible Subroutine Calls
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Solution Overview
Problem
Existing data processing systems face challenges in efficiently executing Java bytecodes as native instructions, particularly in providing flexible target branch addresses for long-range subroutine calls and array bounds checking, leading to increased storage requirements and limited branch predictor capacity.
Innovation Solution
A compare and branch instruction that determines the target branch address from a pre-programmed stored value rather than calculating it within the instruction, allowing for greater flexibility and reducing the need for branch predictor storage, especially useful for array bounds checking in object-oriented programming languages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a compare and branch instruction calculates target branch address from a relative offset within the instruction, then the instruction structure is simple and fixed-size, but the range of target branch addresses is limited
Solution Approach 1:
The target branch address specification is divided into two parts: a base address stored in a pre-programmed location (such as a register or memory) and an offset field within the instruction. This segmentation allows the base address to provide the high-order bits for long-range branching while the offset field provides fine-grained adjustment, thereby extending the reachable address range without increasing overall instruction complexity
Solution Approach 2:
A pre-programmed base address (stored in a register or memory location) acts as an intermediary between the instruction's offset field and the final target branch address. This intermediary enables the instruction to reach addresses beyond what the offset field alone could specify, while keeping the instruction format compact
2Productivity
If bytecodes are translated into native instructions by a JIT compiler, then Java bytecodes can be executed as native instructions, but the translated code size is considerably larger than the original bytecodes
Solution Approach 1:
Multiple operations are merged into a single compare and branch instruction: the comparison of two values (typically array bounds checking) and the conditional branch to an exception handler are combined into one instruction. This reduction in instruction count directly reduces the size of translated code while maintaining execution efficiency
Solution Approach 2:
The compare and branch instruction serves multiple functions: it performs bounds checking, determines branch condition, and executes the branch in a single operation. This multi-functionality reduces the number of instructions needed in translated code, thereby reducing overall code size while maintaining productivity
3Reliability
If branch predictor storage is used to cache branch results, then branch prediction accuracy is improved, but the storage capacity is limited and gets occupied by infrequent branches
Solution Approach 1:
The target branch address is extracted from the pre-programmed base address rather than being fully specified within the instruction's offset field. This extraction allows branch predictor storage to focus on caching the relatively small offset values and branch outcomes for frequent branches, while the base addresses for infrequent exception handlers are obtained directly from their storage locations without occupying predictor capacity
Data Source
AI summary
A data processing system is provided that includes an instruction decoder 20 responsive to a compare and branch instruction CHKA.X that performs a comparison between first and second values stored in first and second registers Rn, Rm respectively. A target branch address is determined from a pre-programmed stored value and a branch to a sub-routine is performed in dependence upon a result of the comparison.