Tree-Structured Comparison Circuit for Memory Error Checking

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Solution Overview

Problem

The increasing number of failed memory cells in semiconductor devices due to high integration levels leads to reduced production yield and difficulty in ensuring large memory capacity, necessitating effective error correction and testing solutions.

Innovation Solution

A comparison circuit with a tree structure comprising multiple first and second logic circuits that execute exclusive OR and NOR operations to determine if the number of input signals at a specific logic level is even or odd, generating a comparison signal to aid in error correction and testing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If high integration levels are employed to increase memory capacity, then memory capacity is improved, but the number of failed memory cells increases

Engineering Contradiction:

Improvememory capacityVSAvoidnumber of failed memory cells

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The comparison circuit is divided into multiple first logic circuits and second logic circuits arranged in a tree structure. Each logic circuit processes a subset of input signals, and their results are combined to determine the final comparison output. This segmentation allows the circuit to handle larger numbers of input signals while maintaining reliability through distributed processing.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Internal nodes in the tree structure serve as intermediaries that combine results from multiple logic circuits. These intermediate comparison results are processed through successive levels of logic circuits until the final comparison signal is generated, enabling systematic error detection across many input signals.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Measurement precision

If the number of logic circuits is increased to improve comparison accuracy, then measurement precision is improved, but device complexity increases

Engineering Contradiction:

Improvecomparison accuracyVSAvoidnumber of logic circuits

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The logic circuits are arranged in a tree structure that adds a dimensional organization to the comparison process. Instead of a flat configuration, the hierarchical tree structure allows multiple logic circuits to work in parallel across different levels, improving comparison accuracy while managing complexity through structured organization.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Multiple first logic circuits and second logic circuits are merged into a unified tree structure where their outputs are combined at internal nodes. This merging allows the circuit to leverage the collective processing power of multiple logic circuits to improve comparison accuracy while sharing common resources and reducing overall complexity.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9966121B2Comparison circuits and semiconductor devices employing the same

Publication Date: 2018.05.08 SK HYNIX INC

AI summary

A comparison circuit may be provided. The comparison circuit may include a number of first logic circuits and a number of second logic circuits. The first logic circuits and second logic circuits may be configured to compare logic levels of a plurality of input signals with each other to generate a comparison signal having a first logic level if the number of input signals have an even number of input signals at a second logic level.