CMOS Image Sensor Comparison Circuit Parasitic Capacitor Conversion
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Solution Overview
Problem
The transmission efficiency in CMOS image sensor comparison circuits is limited by the ratio of predetermined capacitors to parasitic capacitors, which affects the conversion of optical images into electrical signals, leading to noise in digital signals.
Innovation Solution
The comparison circuit incorporates a layout change to convert parasitic capacitors at floating nodes into input capacitors, increasing the capacitance of the input capacitors and reducing the capacitance of parasitic capacitors, thereby enhancing transmission efficiency through the use of additional pixel and ramp capacitors connected in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If parasitic capacitors are present at floating nodes in the comparison circuit, then the circuit can be manufactured with standard CMOS processes, but the transmission efficiency is reduced due to the ratio of predetermined capacitors to parasitic capacitors
Solution Approach 1:
The patent converts the harmful parasitic capacitors formed at floating nodes into beneficial input capacitors by changing the circuit layout. Specifically, the parasitic capacitors that naturally form between the floating node and peripheral routing lines are intentionally utilized as part of the input capacitor structure, thereby eliminating their harmful effect and converting them into useful capacitance for signal transmission.
Solution Approach 2:
The patent changes the layout parameters of the comparison circuit to increase the capacitance of input capacitors. By modifying the physical arrangement and connecting the parasitic capacitor in parallel with the input capacitor, the total capacitance value is increased, which improves transmission efficiency without requiring additional manufacturing steps.
2Reliability
If the capacitance of input capacitors is increased to improve transmission efficiency, then noise in digital signals is reduced, but the device complexity increases due to additional capacitors and layout changes
Solution Approach 1:
The patent employs self-service by utilizing the parasitic capacitors that naturally form during the CMOS manufacturing process. These parasitic elements, which would normally require additional compensation or elimination, are automatically utilized as part of the input capacitor structure, eliminating the need for separate components or complex layout adjustments.
Solution Approach 2:
The patent merges the parasitic capacitor with the input capacitor by connecting them in parallel through layout design. This combination increases the total capacitance value while using the same physical space and manufacturing structures, thereby improving transmission efficiency without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improvement increases the capacitance of input capacitors, leading to enhanced transmission efficiency and reduced noise in digital signals, thus improving the overall performance of the image sensor.
Implementation Method 1
a parasitic capacitor, among the parasitic capacitors, formed at a floating node between the input capacitor and the amplifier is converted into an input capacitor by changing a layout of the comparison circuit to increase capacitance of the input capacitor
Data Source
AI summary
A comparison circuit that includes an input sampling capacitor and an image sensor including the same are provided. The comparison circuit includes an amplifier configured to receive a pixel signal and a ramp signal to perform a correlated double sampling operation, a first pixel capacitor connected to the amplifier through a first floating node and configured to transmit the pixel signal, a first ramp capacitor connected to the amplifier through a second floating node and configured to transmit the ramp signal, a second pixel capacitor connected in parallel to the first pixel capacitor, and a second ramp capacitor connected in parallel to the first ramp capacitor, wherein the second pixel capacitor is formed between the first floating node and first peripheral routing lines, and the second ramp capacitor is formed between the second floating node and second peripheral routing lines.