Compensated Phase Detector for DFE Clock Jitter Reduction
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Solution Overview
Problem
At high data rates, decision-feedback equalization (DFE) techniques face challenges in accurately generating clock signals due to increased clock jitter, which is influenced by DFE delays, leading to sub-optimal phase detection in clock generators.
Innovation Solution
A method and receiver architecture that samples received signals using data and transition clocks, performs DFE correction with an effective delay, and generates phase updates based on DFE detected data bits and corrected transition data, using a weighted threshold calculated from prior-received data bits to address DFE delay impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If DFE correction is performed within one baud-period at very high data rates, then data detection accuracy is improved, but circuit design complexity and accuracy become difficult to achieve
Solution Approach 1:
The patent segments the DFE correction process by separating the data sampling and DFE correction operations from the clock generation operations. The data path performs DFE correction within one baud-period, while the clock generation path uses transition samples that are processed independently, allowing each path to be optimized separately for its specific requirements.
Solution Approach 2:
The patent introduces transition samples as an intermediary element that bridges the data path and clock generation path. These transition samples are captured at specific times and processed through a dedicated path that accounts for DFE delay, serving as a mediator that allows accurate clock generation without requiring the entire DFE correction to complete within one baud-period.
2Measurement precision
If DFE correction is performed within one baud-period, then data detection is improved, but clock jitter increases due to DFE delay impacts on phase detection
Solution Approach 1:
The patent applies local quality by treating the clock generation path differently from the data path. Specifically, the transition sample processing incorporates DFE delay compensation tailored to the clock generation requirements, while the data detection path maintains its standard DFE correction without such compensation, as each path has different quality requirements.
Solution Approach 2:
The patent implements feedback mechanisms in the clock generation path by using previously detected data bits to calculate weighted thresholds for transition sample processing. This feedback from the data detection path to the clock generation path allows the system to compensate for DFE delay effects on phase detection, reducing clock jitter.
3Device complexity
If transition samples are processed using standard slicing without DFE delay compensation, then clock generation is simplified, but phase detection accuracy deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-calculating weighted thresholds based on previously detected data bits before processing transition samples for clock generation. This preliminary computation of threshold values allows the transition sample processing to account for DFE delay effects without requiring complex real-time compensation, maintaining simplicity while improving accuracy.
Data Source
AI summary
A method and apparatus generating one or more clock signals in a receiver employing decision-feedback equalization (DFE). A received signal is sampled by a data clock and a transition clock, generating a data sample signal and a transition sample signal, respectively. A DFE correction is performed by DFE circuitry on the data sample signal to generate DFE detected data bits. The transition sample signal is sliced using a weighted threshold value to generate transition data bits. One or more phase updates of the data clock and the transition clocks are in response to the DFE detected data bits and the transition data bits. The weighted threshold is calculated from at least one of the prior-received DFE detected data bits. In one embodiment, the DFE detection may also be dependent on an effective delay (λ) of the DFE circuit in relation to the received signal baud-period, T.