Compensated Triple Gate Driving Circuit for Display Panel
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Solution Overview
Problem
Existing gate driver on array (GOA) circuits in display technology face challenges in reducing variation in output delays and discharging rates among gate-driving signals, which affects the quality of the display by causing undesired voltage drops in the pull-up node, leading to inconsistent gate line signal delays and data input charging rates.
Innovation Solution
A compensated triple gate driving circuit is introduced, featuring a cascaded structure of GOA units with a capacitor connected between the second set of output terminals of the second GOA unit and the pull-up node of the first GOA unit, allowing for a compensation signal to be transferred, which maintains the output transistors in an ON state and reduces discharge time by boosting the voltage levels during delay times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common pull-up node is used to control multiple output transistors, then the device complexity is reduced, but the output delays and discharging rates vary among multiple gate-driving signals
Solution Approach 1:
The patent divides the GOA circuit into multiple independent GOA units, each with its own pull-up node and output transistors. This segmentation allows each unit to operate independently with consistent timing, eliminating the delay variations that occur when multiple transistors share a common pull-up node.
Solution Approach 2:
The patent introduces a compensation capacitor connected between the output terminal of the second GOA unit and the pull-up node of the first GOA unit. This intermediary capacitor provides voltage compensation to the pull-up node, ensuring consistent voltage levels and discharge rates across multiple gate-driving signals while maintaining the simplified circuit structure.
2Length of moving object
If the number of transistor devices is limited, then the frame width is narrowed, but the waveform stability of gate-driving signals deteriorates
Solution Approach 1:
The patent segments the GOA circuit into multiple units, each with dedicated pull-up nodes and output transistors. This segmentation allows the circuit to maintain waveform stability with fewer transistors per unit, thereby narrowing the overall frame width while preserving signal quality.
Solution Approach 2:
The compensation capacitor creates a feedback mechanism where the output signal from the second GOA unit feeds back to the pull-up node of the first GOA unit. This feedback compensates for voltage drops and maintains waveform stability, allowing reduced transistor counts without sacrificing reliability.
3Productivity
If gate-driving signals are outputted sequentially with delays, then the data input charging rate is improved, but the discharge time of gate-driving signals increases
Solution Approach 1:
The patent uses the compensation capacitor to provide preliminary voltage boost to the pull-up node before the gate-driving signal needs to discharge. This preliminary action maintains the voltage level during the delay period, reducing the discharge time while allowing sequential outputting for improved data charging rates.
Solution Approach 2:
The patent changes the voltage parameter at the pull-up node by introducing the compensation capacitor that maintains a higher voltage level during the delay period. This parameter change allows the gate-driving signals to be outputted sequentially with shorter discharge times, improving overall productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces the discharge time of gate-driving signals, improving the stability and efficiency of gate line signal transmission, thereby enhancing the display quality by maintaining the voltage levels and ensuring accurate data input across the display panel.
Implementation Method 1
a capacitor connected from one in the second set of three output terminals of the second GOA unit to the pull-up node of the first GOA unit
Data Source
AI summary
The present application discloses a gate driver on array (GOA) circuit of a display panel. The GOA circuit includes a first GOA unit comprising a unit-circuitry structure having a pull-up node commonly coupled to three output transistors to control outputting of a first set of three gate-driving signals respectively to a first set of three gate lines associated with the display panel. The GOA circuit additionally includes a second GOA unit comprising a substantially same unit-circuitry structure cascaded with the first GOA unit and configured to control outputting a second set of three gate-driving signals respectively to a second set of three gate lines associated with the display panel. Moreover, the GOA circuit includes a capacitor connected from one in the second set of three output terminals of the second GOA unit to the pull-up node of the first GOA unit.