Compensating Wire Routing for Maskless Exposure Chip Deviation
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Solution Overview
Problem
In traditional maskless exposure technologies, chip deviation during die bonding leads to asymmetry or skewness, making it difficult to connect lead wires between heterogeneous chips of different shapes and sizes, which can result in short circuits.
Innovation Solution
A chip deviation correction method for maskless exposure machines that calculates a compensating wire to connect skewed lead wires across a separating boundary, correcting the chip deviation error during die bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional maskless exposure technology is used for heterogeneous chips, then chip bonding can be performed, but chip deviation causes lead wire connection difficulties and short circuits
Solution Approach 1:
The patent performs preliminary calculation of compensating wires before actual exposure. The system calculates the deviation of each chip from its intended position, determines the necessary compensation, and pre-generates the corrected exposure pattern. This preliminary correction action ensures that even when chips are bonded with positional deviations, the lead wires will still connect accurately to the corresponding pads on adjacent chips, preventing short circuits and connection failures.
2Productivity
If direct lead wire connection between heterogeneous chips is attempted, then connection speed is maintained, but chip asymmetry causes lead wire interference and short circuits
Solution Approach 1:
The patent applies local quality correction by calculating individual compensating wires for each chip based on its specific positional deviation. Rather than using a uniform connection approach for all chips, the system determines the unique compensation needed for each chip's lead wire routing. This localized correction ensures that lead wires from chips with different deviations are adjusted appropriately, preventing interference and short circuits while maintaining connection efficiency.
3Manufacturing precision
If compensating wires spanning separating boundaries are calculated, then chip deviation error is corrected, but calculation complexity increases
Solution Approach 1:
The patent segments the correction problem by dividing it into discrete steps: first calculating the positional deviation of each chip from its intended location, then determining the separating boundary between adjacent chips, and finally calculating the compensating wire that spans the boundary. This segmentation of the complex correction task into manageable sequential steps makes the overall system more tractable while achieving high correction accuracy for chip deviation errors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively corrects chip deviation errors by forming a continuous uninterrupted wiring between chips, preventing short circuits and ensuring accurate connection of lead wires.
Implementation Method 1
a digital pattern is used to output and project ultraviolet light with a corresponding pattern onto the wafer, such that the portion of a photoresist layer projected with the ultraviolet light will be melted easily
Data Source
AI summary
A chip deviation correction method for maskless exposure machines includes the steps of calculating the bonding positions of chips on a substrate to define the coordinates of the chips on the substrate, creating a separating boundary among the chips according to the coordinates of the chips on the substrate to form plural of bonding areas for accommodating the chips, calculating a lead wire of the chips in the bonding area and a compensating wire which spans across the separating boundary between each lead wire and the lead wire of the corresponding adjacent chip according to the calculated lead wire; and forming a digital exposed layer according to each of the lead wires and each of the compensating wires.