Compensation Capacitors in DRAM Wiring Structures
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Solution Overview
Problem
The challenge in semiconductor device design is to increase integration density and performance while minimizing power dissipation and heat generation, particularly in DRAM devices, where conventional methods for forming compensation capacitors at small dimensions are complex and inefficient, and the integration of redistribution layers increases chip size and power consumption.
Innovation Solution
Incorporating a compensation capacitor within the wiring structure between the integrated redistribution layer (iRDL) and an underlying wiring structure, allowing for the capacitor to be formed at desired small dimensions without increasing the device footprint, using a multilevel wiring structure with the iRDL located above the underlying wiring structures, and employing specific material deposition and patterning techniques to optimize capacitor design and placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If compensation capacitors are formed using conventional techniques in small openings, then the capacitor footprint is reduced, but the manufacturing complexity and difficulty increase
Solution Approach 1:
The patent transitions from planar capacitor formation to three-dimensional formation by depositing materials conformally on the sidewalls of trenches. This vertical dimensionality allows the capacitor to achieve sufficient surface area in a compact footprint while using standard deposition techniques, thereby reducing manufacturing complexity.
Solution Approach 2:
The capacitor structure is nested within the wiring structure by forming the capacitor electrodes and dielectric material within trenches defined by the interlayer insulating material. This nesting allows the capacitor to occupy space that would otherwise be unused, reducing overall footprint without requiring separate fabrication processes.
2Loss of energy
If an integrated redistribution layer is used to provide power, then power dissipation and heat generation are reduced, but the chip size increases
Solution Approach 1:
The iRDL serves multiple functions: it provides power distribution, acts as a structural layer for the capacitor formation, and enables compact wiring routing. This multi-functionality allows the iRDL to reduce power dissipation while maintaining a compact chip size, as it eliminates the need for separate dedicated power delivery structures.
Solution Approach 2:
The patent merges the power distribution function with the capacitor formation structure by integrating the capacitor within the iRDL layer. This consolidation allows the power delivery network and capacitor to share the same physical space, reducing overall chip size while maintaining low power dissipation through the iRDL's low-resistivity material.
3Area of stationary object
If the compensation capacitor is formed at small dimensions, then the device footprint is reduced, but the capacitor surface area decreases
Solution Approach 1:
The patent resolves this contradiction by moving the capacitor surface area generation from the planar dimension to the vertical dimension. Conformal deposition on trench sidewalls creates large surface area within a small footprint, achieving both compact device size and sufficient capacitor area for noise compensation.
Data Source
AI summary
An apparatus comprising first and second interconnections spaced apart from one another, an interlayer insulating material over the first and second interconnections, first and second contacts in the interlayer insulating material and spaced apart from one another, third and fourth interconnections over the interlayer insulating material and spaced apart from one another, and compensation capacitors in a capacitor region. The third interconnections are coupled with the first interconnections through the first contacts and the fourth interconnections are coupled with the second interconnections through the second contacts. The compensation capacitors comprise lower electrodes over the interlayer insulating material, dielectric materials over the lower electrodes, and upper electrodes over the dielectric materials. The lower electrodes comprise edge portions in contact with the second contacts. The third interconnections are elongated over the dielectric materials and are configured to provide elongated portions as the upper electrodes of the compensation capacitors. Related methods, memory devices, and electronic systems are disclosed.