Compensation Circuit for Parallel Power Switches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional power converter circuits face inefficiencies due to overvoltage issues and dynamic unbalance in parallelized power electronic switches, leading to reduced performance and premature aging, especially when trying to manage parasitic inductances and varying bus voltages.
Innovation Solution
A compensation circuit that samples and adjusts the voltage induced across parasitic inductances during turn-on and turn-off of power electronic switches, feeding this feedback to the gate driver to control the rate of current change, thereby balancing switching losses and overvoltage across parallelized switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If fast turn-off of power electronic switches is used to reduce switching losses, then switching losses are reduced, but overvoltage is generated in parasitic inductances
Solution Approach 1:
The patent implements a feedback mechanism where the voltage induced across parasitic inductance is sampled and fed back to the gate driver. This feedback signal dynamically adjusts the gate voltage to control the rate of current change, enabling fast switching while preventing overvoltage generation through real-time compensation.
Solution Approach 2:
The patent dynamically changes the gate voltage parameter during switching transitions. By adjusting the gate voltage based on the sampled inductance voltage, the system optimizes the switching speed while maintaining overvoltage protection, effectively resolving the contradiction between fast switching and overvoltage prevention.
2Loss of energy
If fast turn-on of power electronic switches is used to reduce switching losses, then switching losses are reduced, but dynamic unbalance occurs in parallelized switches
Solution Approach 1:
The feedback mechanism samples the voltage across parasitic inductance for each parallel switch and provides individual compensation. This ensures that each switch in the parallel configuration experiences balanced switching conditions, preventing dynamic unbalance while maintaining fast switching and reducing overall switching losses.
3Device complexity
If conventional gate driver control is used, then circuit simplicity is maintained, but switching losses increase and efficiency decreases
Solution Approach 1:
The patent introduces an intermediary compensation circuit that includes voltage sampling components and a feedback path to the gate driver. This intermediary mechanism enables dynamic optimization of switching performance without requiring complete redesign of the gate driver architecture, thus reducing switching losses while maintaining reasonable circuit simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces switching losses, manages overvoltage, and balances thermal stress across parallelized power electronic switches, enhancing the overall efficiency and reliability of power converters by dynamically adjusting the gate voltage during both turn-on and turn-off phases.
Implementation Method 1
a first circuit path configured to sample a first portion of a voltage induced across an inductance of the power electronic switch at turn-on of the power electronic switch
Implementation Method 2
Losses in power electronic switches present in conventional power converter circuits are mainly caused by two sources; conduction losses and switching losses
Data Source
AI summary
The present disclosure relates to a compensation circuit for independently controlling turn-on and turn-off of a power electronic switch through a gate driver. The compensation circuit includes a circuit path sampling a first portion of a voltage induced across an inductance of the power electronic switch at turn-on. Another circuit path samples a second portion of the voltage induced across the inductance of the power electronic switch at turn-off. The compensation circuit further includes a gate driver reference connection configured to respectively supply the sampled portions of the voltage during turn-on and turn-off of the power electronic switch. A compensation circuit controlling a first power electronic switch in parallel with a second power electronic switch, a commutation cell and a power converter having a pair of parallel legs, in which each power electronic switch is provided with the compensation circuit, are also disclosed.


