Compensation Gate Driver Clock Waveform Control for Display Devices
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Solution Overview
Problem
In display devices, the compensation gate signal output from the gate driver during the blank period tends to increase in turn-off level due to a longer floating section at the output end, leading to potential issues with the control of initialization and compensation transistors.
Innovation Solution
A display device with a compensation gate driver system that generates compensation gate signals using different clock signals during scan and blank periods, with the first and second compensation gate drivers producing signals with specific waveform delays to maintain the compensation gate signal at a turn-off level during the blank period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the cycle of the clock signal provided to the gate driver is increased during the blank period to reduce power consumption, then power consumption is reduced, but the turn-off level of the compensation gate signal output from the gate driver increases
Solution Approach 1:
The gate driver is divided into two independent gate drivers (first gate driver and second gate driver) that operate in parallel. Each gate driver has its own clock signal input, allowing independent control of their operating cycles. This segmentation enables the system to maintain proper signal levels while reducing overall power consumption by coordinating the activity periods of both drivers.
Solution Approach 2:
The patent employs periodic clock signals with different cycles for the first and second gate drivers. During the blank period, the clock signal cycle is increased (reducing frequency) to lower power consumption, while during the scan period, the original cycle is maintained to ensure proper signal levels. This periodic modulation of clock frequency resolves the contradiction between power savings and signal integrity.
2Use of energy by moving object
If the cycle of the clock signal provided to the gate driver is increased during the blank period, then power consumption is reduced, but the floating section at the output end becomes longer
Solution Approach 1:
By segmenting the gate driver into two independent units, each with its own clock signal control, the patent can manage the floating section duration independently for each driver. This allows one driver to be in a low-power state with extended floating section while the other maintains proper timing, effectively distributing the burden and reducing overall power consumption without excessive floating duration impact.
Solution Approach 2:
The patent changes the clock signal parameters (cycle frequency) dynamically based on the operating period. During the blank period, the clock cycle is increased to reduce power consumption, accepting a longer floating section as a temporary trade-off. During the scan period, the clock cycle returns to its original value, restoring proper timing characteristics. This parameter modulation resolves the contradiction between power savings and floating section duration.
3Use of energy by moving object
If the turn-off level of the compensation gate signal increases during the blank period, then the control of initialization transistor and compensation transistor is affected, but power consumption can be reduced
Solution Approach 1:
The patent divides the gate driver functionality into two independent drivers, each capable of independently controlling the compensation gate signal. During the blank period, one driver can be placed in a low-power mode with reduced activity, while the other driver maintains proper signal levels to ensure correct transistor control. This segmentation allows simultaneous achievement of power reduction and maintained control quality.
Solution Approach 2:
The patent implements periodic operation where the gate drivers alternate or coordinate their activity during blank and scan periods. During the blank period, the clock signal frequency is reduced to save power, but the drivers are periodically activated to refresh or reset the compensation gate signal, preventing excessive drift in turn-off level. During the scan period, full-frequency operation ensures optimal transistor control. This periodic action resolves the contradiction between power consumption and control ease.
Data Source
AI summary
A display device includes: a display panel including pixels connected to compensation gate lines, and a compensation gate driver which supplies compensation gate signals to the display panel. The compensation gate driver includes: a first compensation gate driver which generates the compensation gate signals based on a first-first clock signal and a second-first clock signal and a second compensation gate driver which generates the compensation gate signals based on a first-second clock signal and a second-second clock signal. The first-first clock signal and the second-first clock signal have the same waveform as the first-second clock signal and the second-second clock signal, respectively, during a scan period in which a compensation gate signal is supplied to the display panel, and have different waveforms from the first-second clock signal and the second-second clock signal, respectively, during a blank period in which the compensation gate signal is not supplied to the display panel.