Compensation Implant Mitigates Parasitics in High Resistivity Substrates

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Solution Overview

Problem

Monolithic RF circuits using high resistivity substrates face issues with substrate parasitics, leading to degraded linearity and voltage imbalance due to inversion layers and parasitic p-n junctions, which adversely impact RF signal quality.

Innovation Solution

A method involving a compensation implant region and damaged implant regions in the high resistivity substrate to compensate fixed charges and create carrier traps, reducing the impact of inversion layers and parasitic p-n junctions, thereby improving linearity by forming isolated segments and reducing capacitive coupling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high resistivity substrate is used to reduce substrate parasitics, then substrate resistivity is improved, but inversion layer forms due to fixed positive charges in dielectric layers

Engineering Contradiction:
Improvesubstrate resistivityVSAvoidinversion layer
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A compensation implant region is formed in the high resistivity substrate before the dielectric layer is deposited. This compensation implant region has a doping type and concentration designed to counteract the fixed positive charges that will later be trapped in the dielectric layer, preventing the formation of inversion layers and maintaining high substrate resistivity.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The compensation implant region is created in advance during substrate preparation, establishing a charge balance that will counteract future charge accumulation in dielectric layers. This preliminary action ensures that when dielectric layers are subsequently deposited and traps form, the inversion layer effect is already mitigated.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If large spacing is used to avoid leakage between junctions, then electrical isolation is improved, but device density decreases

Engineering Contradiction:
Improveelectrical isolationVSAvoiddevice density
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Deep dielectric filled trenches are introduced as intermediary structures between junctions at different potentials. These trenches extend deep into the substrate and are filled with dielectric material, providing strong electrical isolation that enables smaller spacing between devices while maintaining reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Instead of increasing horizontal spacing to achieve isolation, the solution extends isolation vertically by creating deep trenches that penetrate deep into the substrate. This dimensional approach allows compact device layout while maintaining electrical isolation through the depth dimension.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If deep dielectric filled trenches are used to reduce spacing, then device density is improved, but parasitic p-n junctions form with inverted charges

Engineering Contradiction:
Improvedevice densityVSAvoidparasitic p-n junctions
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The compensation implant region is formed before creating deep dielectric trenches to preemptively counteract charge accumulation. By establishing the compensation doping profile in advance, the patent prevents the formation of parasitic p-n junctions that would otherwise occur when deep trenches create isolated segments with trapped charges.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The compensation implant region modifies the electrical parameters (doping concentration and type) of the substrate in strategic locations. By changing these parameters before trench formation, the patent ensures that when deep trenches are created, the resulting isolated segments do not form harmful parasitic junctions.

Inventive Principle:
Principle #35Parameter changes

4Reliability

If compensation implant region is formed to prevent inversion layer, then substrate resistivity is maintained, but device fabrication complexity increases

Engineering Contradiction:
Improvesubstrate resistivityVSAvoidfabrication process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The compensation implant region formation is merged with existing fabrication steps. The compensation implant is performed using the same ion implantation equipment and processes already required for device fabrication, combining the parasitic mitigation function with standard manufacturing operations to minimize additional complexity.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively mitigates substrate parasitics, enhancing the linearity of RF signals by eliminating parasitic p-n junctions and reducing voltage-dependent capacitive coupling, leading to improved performance in RF circuits.

Implementation Method 1

fixed positive charges in the dielectric layers on top of the high resistivity substrate, can induce an inversion layer in the high resistivity substrate

Methodology Applied
Scientific EffectFixed positive charges inducing inversion layer: Electrostatic Induction

Implementation Method 2

due to the low background doping of the high resistivity substrate, the fixed positive charges can cause an accumulation of high mobility carriers of opposite polarity under the dielectric layer

Methodology Applied
Scientific EffectCarrier accumulation due to low background doping: Electrical Accumulator

Implementation Method 3

A method involving a compensation implant region and damaged implant regions in the high resistivity substrate to compensate fixed charges and create carrier traps

Methodology Applied
Scientific EffectCarrier trapping: Electrical Accumulator

Implementation Method 4

A deep dielectric filled trench in the high resistivity substrate can significantly reduce the spacing to allow smaller products

Methodology Applied
Scientific EffectElectrical isolation through dielectric filling: Dielectric

Implementation Method 5

the capacitive coupling between one or more of the metal layers and the high resistivity substrate would also become voltage dependent

Methodology Applied
Scientific EffectCapacitive coupling: Capacitance

Data Source

PatentUS9941353B2Structure and method for mitigating substrate parasitics in bulk high resistivity substrate technology
Publication Date: 2018.04.10 NEWPORT FAB LLC
  • US9941353B2 patent drawing
  • US9941353B2 patent drawing
  • US9941353B2 patent drawing

AI summary

A structure includes a field isolation region in a high resistivity substrate, a compensation implant region under the field isolation region in the high resistivity substrate, where the compensation implant region is configured to substantially eliminate a parasitic p-n junction under the field isolation region. The parasitic p-n junction is formed between trapped charges in the field isolation region and the high resistivity substrate. The compensation implant region includes a charge of a first conductivity type to compensate a parasitic charge of a second conductivity type under the field isolation region. The compensation implant region is configured to improve linearity of RF signals propagating through a metallization layer over the field isolation region. The structure further includes a deep trench extending through the field isolation region and the compensation implant region, and a damaged region adjacent the deep trench.