Compensation Layer Architecture for Wafer Hybrid Bond Alignment

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Solution Overview

Problem

Current wafer-to-wafer hybrid bonding techniques face challenges in achieving accurate bonding pad alignment, leading to yield losses and increased costs due to misalignment errors and defects from die singulation and thickness variations, especially in heterogeneous packages.

Innovation Solution

The use of compensation layers with adaptive patterning techniques to measure and correct individual KGD placement errors, forming hybrid bond layers that ensure symmetric bonding and continuous electrical pathways, thereby improving bonding pad alignment and reducing defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If wafer-to-wafer hybrid bonding is performed without compensation layers, then the bonding process is simpler and faster, but bonding pad alignment accuracy deteriorates due to misalignment errors from die singulation and thickness variations

Engineering Contradiction:
Improvebonding pad alignment accuracyVSAvoidpackaging architecture complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent introduces compensation layers as intermediary elements between the bonding pads of opposing wafers. These compensation layers serve as mediators that absorb and correct for misalignment errors, thickness variations, and warpage. The compensation layers include compensatory features such as dummy bonding pads and adjustable interconnect structures that can be tuned to match alignment deviations, thereby enabling accurate bonding despite variations in die dimensions and placement precision.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs parameter changes by making the compensation layer characteristics adjustable and configurable. The compensation layers can be designed with varying thicknesses, material compositions, and feature geometries to compensate for different types and magnitudes of misalignment. The interconnect structures within the compensation layers can be adjusted in length, width, and routing to optimize alignment correction for specific die variations, allowing the system to adapt to different packaging scenarios.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If compensation layers with adaptive patterning are used to correct individual KGD placement errors, then bonding pad alignment and manufacturing yield improve, but the packaging architecture and process complexity increase

Engineering Contradiction:
Improvemanufacturing yieldVSAvoidpackaging architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements self-service through adaptive patterning techniques that automatically measure the actual placement positions of known-good dies and use this information to configure the compensation layers accordingly. The system performs self-measurement of die locations using optical or other detection methods, then self-adjusts the compensation layer patterns to correct for measured deviations. This eliminates the need for manual measurement and correction, allowing the packaging process to self-correct for placement errors and thereby improve yield while managing complexity through automation.

Inventive Principle:
Principle #25Self-service

3Measurement precision

If precise measurement and correction of individual KGD placement errors is performed, then bonding pad alignment accuracy improves, but measurement and process complexity increase

Engineering Contradiction:
ImproveKGD placement measurement accuracyVSAvoidmeasurement process complexity
Core Design Contradiction:
Measurement precisionVSDifficulty of detecting and measuring

Solution Approach 1:

The patent applies preliminary action by performing measurement and compensation layer configuration in advance before the actual hybrid bonding process. The placement of known-good dies is measured and recorded during the assembly process, and the compensation layers are designed and configured based on these pre-measured positions before bonding occurs. This preliminary measurement and preparation allows the bonding process itself to proceed with standard precision requirements, as the compensation layers are already tailored to correct for the specific placement variations observed.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250006695A1Packaging architecture including compensation layers for wafer-scale known-good-die to known-good-die hybrid bonding
Publication Date: 2025.01.02 INTEL CORP
  • US20250006695A1 patent drawing
  • US20250006695A1 patent drawing
  • US20250006695A1 patent drawing

AI summary

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer with a first die having a first contact; a second die having a second contact; and a pad layer, on the first and second dies, including a first pad and a second pad, where the first pad is coupled to and offset from the first contact in a first direction, and the second pad is coupled to and is offset from the second contact in a second direction different than the first direction; and a second layer including a third die having third and fourth contacts, where the first layer is coupled to the second layer by metal-to-metal bonds and fusion bonds, the first contact is coupled to the third contact by the first pad, and the second contact is coupled to the fourth contact by the second pad.