Compensation Memory Lookup Tables for Integrated PLD Power Control

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Solution Overview

Problem

Programmable logic devices (PLDs) face limitations in handling high-voltage and high-current power applications due to the constraints of their internal I/O pins, requiring external discrete high-voltage power MOSFETs that increase cost and board space.

Innovation Solution

Integration of a memory block with lookup tables and a signal wrapper in a PLD to generate compensated output signals, allowing programmable adjustment of pre-populated data for improved I/O performance and efficiency in power applications, such as power regulators and converters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If external discrete high-voltage power MOSFETs are added to expand PLD application to high-voltage/current power applications, then the power handling capability is improved, but the cost and board space increase

Engineering Contradiction:

Improvepower handling capabilityVSAvoidboard space

Core Design Contradiction:

PowerVSArea of stationary object

Solution Approach 1:

The patent integrates the power MOSFET directly into the PLD chip, merging previously separate components (PLD controller and external power MOSFET) into a single unified device. This eliminates the need for external discrete MOSFETs, reducing board space while maintaining high-voltage and high-current power handling capabilities through dedicated power output pins designed for such applications.

Inventive Principle:

Principle #5Merging (Combining)

2Power

If external discrete high-voltage power MOSFETs are added to expand PLD application to high-voltage/current power applications, then the power handling capability is improved, but the cost increases

Engineering Contradiction:

Improvepower handling capabilityVSAvoidcost

Core Design Contradiction:

PowerVSEase of manufacture

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The integrated PLD device serves multiple functions simultaneously: it acts as both a programmable logic controller and a high-voltage power switch. The device can handle various power application types (power regulator, power converter) and provides both digital control capabilities and analog power switching, reducing the need for multiple separate components and thereby lowering overall system cost.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Area of stationary object

If the PLD I/O pins are used for power applications, then the board space is reduced, but the voltage and current handling capability is insufficient

Engineering Contradiction:

Improveboard spaceVSAvoidvoltage and current handling capability

Core Design Contradiction:

Area of stationary objectVSPower

Solution Approach 1:

The patent implements different pin types with specialized characteristics for different functions. Standard I/O pins maintain their original voltage and current limitations for general-purpose digital operations, while dedicated power output pins are designed with enhanced local quality—specifically higher voltage and current handling capabilities—through specialized internal circuitry and packaging designed for power applications.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent segments the I/O pin functionality into distinct categories: standard I/O pins for digital control and communication, and dedicated power output pins for high-voltage and high-current power switching. This segmentation allows each pin type to be optimized for its specific function, enabling the device to handle power applications effectively while maintaining compatibility with standard digital interfaces.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10396800B2Compensation memory (CM) for power application

Publication Date: 2019.08.27 XMOS

AI summary

A memory block integrated in a programmable logic device (PLD) is disclosed. The memory block includes: one or more lookup tables storing pre-populated data. The PLD includes a programmable fabric and a signal wrapper configured to provide signals between the memory block and the programmable fabric. The memory block is configured to receive input signals from the signal wrapper and generate output signals to the signal wrapper by looking up the pre-populated data corresponding to the input signals. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper.