Compensation Memory Lookup Tables for PLD Power I/O
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Solution Overview
Problem
Programmable logic devices (PLDs) face limitations in handling high-voltage and high-current power applications due to the constraints of their internal I/O pins, requiring external discrete high-voltage power MOSFETs that increase cost and board space.
Innovation Solution
Integration of a memory block with lookup tables and a signal wrapper in a PLD to generate compensated output signals, allowing pre-populated data to be programmably changed and loaded, enabling efficient signal processing and reducing the need for external components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If external discrete high-voltage power MOSFETs are added to expand PLD application to high-voltage/current power applications, then the power handling capability is improved, but the cost and board space increase
Solution Approach 1:
The patent integrates the power MOSFET directly into the PLD chip, merging the programmable logic device and the power switch into a single integrated component. This eliminates the need for external discrete MOSFETs, reducing board space and device complexity while maintaining high-voltage and high-current power handling capability through dedicated high-voltage I/O pins and integrated power blocks
2Power
If external discrete high-voltage power MOSFETs are added to expand PLD application to high-voltage/current power applications, then the power handling capability is improved, but the cost increases
Solution Approach 1:
The integration of power MOSFETs into the PLD chip reduces the total component count and assembly requirements, lowering manufacturing costs. The single-chip integration eliminates the need for separate packaging and mounting of external MOSFETs, reducing overall system cost while providing high-voltage power capability through dedicated internal power blocks
3Device complexity
If the PLD uses internal I/O pins for power applications, then the device complexity is reduced, but the power handling capability is limited
Solution Approach 1:
The patent implements local quality by creating specialized high-voltage I/O pins and dedicated power blocks within the PLD chip. These localized high-voltage capable regions provide enhanced power handling capability (up to 50V and 50mA per pin) while the rest of the device maintains standard low-voltage logic operations, thus improving power capability without requiring complete device redesign
Data Source
AI summary
A memory block integrated in a programmable logic device (PLD) is disclosed. The memory block includes: one or more lookup tables storing pre-populated data. The PLD includes a programmable fabric and a signal wrapper configured to provide signals between the memory block and the programmable fabric. The memory block is configured to receive input signals from the signal wrapper and generate output signals to the signal wrapper by looking up the pre-populated data corresponding to the input signals. The pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper.