Compensation Structure for Symmetric MOSFET Output Charge

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Solution Overview

Problem

Semiconductor devices with power semiconductor switching devices face high switching losses due to asymmetrical charge/discharge behavior and energy losses in the reverse blocking mode, which are not effectively addressed by existing compensation structures.

Innovation Solution

The semiconductor device incorporates a compensation structure with a drift zone that includes a non-depletable extension zone and a low-charged edge portion, combined with smoothed vertical dopant profiles, which reduces the difference between charging and discharging gradients by less than 5% above the depletion voltage, minimizing energy stored in the output capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a compensation structure is added to the drift zone, then the reverse blocking characteristics are improved and dopant concentration can be increased, but the device complexity increases

Engineering Contradiction:
Improvereverse blocking characteristicsVSAvoidcompensation structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by modifying the dopant concentration profile in the drift zone through a compensation structure. Specifically, it introduces a non-depletable extension zone with a controlled dopant concentration that differs from the surrounding drift zone, allowing the device to achieve better reverse blocking characteristics while maintaining acceptable forward conduction properties. This parameter modification enables higher overall dopant concentration without adversely affecting reverse blocking performance.

Inventive Principle:
Principle #35Parameter changes

2Power

If the dopant concentration in the drift zone is increased, then the forward conduction capability is improved, but the reverse blocking characteristics deteriorate

Engineering Contradiction:
Improveforward conduction capabilityVSAvoidreverse blocking characteristics
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent applies local quality by creating a non-depletable extension zone within the drift zone that has a specific dopant concentration profile different from the rest of the drift zone. This localized modification allows the majority of the drift zone to maintain higher dopant concentration for improved forward conduction, while the non-depletable extension zone specifically addresses reverse blocking by providing a controlled depletion behavior. The local structural differentiation enables simultaneous optimization of both forward and reverse characteristics.

Inventive Principle:
Principle #3Local quality

3Reliability

If asymmetrical charge/discharge behavior is present, then the device can operate in reverse blocking mode, but switching losses increase

Engineering Contradiction:
Improvereverse blocking mode operationVSAvoidswitching losses
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies preliminary action by designing the non-depletable extension zone to pre-establish a controlled charge distribution that facilitates more symmetrical charge and discharge behavior during switching operations. The extension zone's specific dopant profile prepares the drift zone to deplete and recharge more uniformly, reducing the asymmetry that causes energy losses. This preliminary structural arrangement minimizes the energy stored in output capacitance during reverse blocking, thereby reducing switching losses.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240413198A1Semiconductor Device with Compensation Structure
Publication Date: 2024.12.12 INFINEON TECH AUSTRIA AG
  • US20240413198A1 patent drawing
  • US20240413198A1 patent drawing
  • US20240413198A1 patent drawing

AI summary

A switched-mode power supply includes a power semiconductor device that includes a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones, wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device, wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.