Compiler Placement of Arithmetic Operators in Programmable Logic
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Solution Overview
Problem
High-level language compilers for programmable logic devices are limited in placing arithmetic operators, typically using only one type (either in DSP blocks or logic fabric) due to differing routing delays, which complicates achieving optimal performance and area efficiency.
Innovation Solution
The compiler determines the placement of arithmetic operators in both DSP blocks and logic fabric regions, optimizing the data flow graph by scoring and iteratively adjusting placements to minimize routing delays and area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the compiler uses only one type of arithmetic operator (either in DSP blocks or logic fabric), then routing delay consistency is maintained, but resource utilization efficiency and area optimization are limited
Solution Approach 1:
The patent implements dynamic placement strategies where the compiler can adaptively choose between DSP blocks and logic fabric based on operational requirements. The system dynamically adjusts operator placement during compilation rather than being statically constrained to one type, enabling optimal resource utilization while managing complexity through structured decision-making frameworks.
Solution Approach 2:
The patent applies local quality by allowing different regions of the programmable device to have different operator types based on specific functional requirements. DSP blocks are used in regions requiring high-performance arithmetic operations, while logic fabric is used in regions requiring flexibility or lower performance, optimizing overall device utilization without requiring uniformity across the entire device.
2Area of stationary object
If the compiler places arithmetic operators in both DSP blocks and logic fabric, then area efficiency and resource optimization improve, but routing delay variations increase
Solution Approach 1:
The patent incorporates feedback mechanisms where the compiler evaluates routing delays and performance metrics after initial placement, then iteratively adjusts operator positions. The system uses delay measurements and timing analysis to feedback into the placement algorithm, refining positions to balance area efficiency with timing consistency, ensuring that operators in both DSP blocks and logic fabric are optimally positioned.
Solution Approach 2:
The patent performs preliminary routing delay analysis and placement optimization during the compilation phase before actual device operation. By pre-calculating and pre-positioning operators to account for routing delay variations, the system proactively addresses timing consistency issues rather than reacting to them during runtime, enabling mixed placement while maintaining reliability.
3Speed
If the compiler optimizes for minimal routing delays, then performance improves, but area consumption increases
Solution Approach 1:
The patent applies partial optimization by focusing routing delay minimization only on critical paths rather than all operator placements. The compiler identifies performance-critical arithmetic operators and optimizes their placement for minimal routing delays, while allowing non-critical operators to be placed more densely in available areas, thus achieving performance improvement without proportionally increasing overall area consumption.
Data Source
AI summary
Methods and systems are described for placing arithmetic operators on a programmable integrated circuit device (e.g., a PLD). Placement of arithmetic operators of a data flow graph in one of multiple regions (e.g., a region of DSP circuitry blocks or a region of logic fabric circuitry) on the programmable integrated circuitry device may be determined (e.g., randomly). A score related to the performance of the graph (e.g., a score related to data flow graph routing delays or area consumed by the data flow graph) may be determined and this process may be repeated after one of the arithmetic operators of the data flow graph is moved. The placement of arithmetic operators that corresponds to the best value for the score related to the performance of the data flow graph may be stored. Accordingly, more arithmetic operators may be included on a programmable integrated device than in conventional devices.