Compiler Instruction Distribution for Auxiliary Processors
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Solution Overview
Problem
Existing compilation techniques for networked processing systems fail to efficiently distribute instructions across multiple processors with distinct capabilities and resource connectivity, leading to suboptimal performance.
Innovation Solution
A compilation technique that includes specific instructions in an executable for auxiliary processors, directing them to execute instructions targeting resources with affinity, thereby optimizing execution efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing compilation techniques are used for networked processing systems, then the system can execute instructions on multiple processors, but the instructions are not efficiently distributed across processors with distinct capabilities and resource connectivity, leading to suboptimal performance
Solution Approach 1:
The compilation technique segments instructions into different categories based on their resource targets. The compiler analyzes each instruction to determine which auxiliary processor should execute it, dividing the instruction set into groups that will be distributed to different processors based on resource affinity. This segmentation enables efficient distribution without requiring complex runtime decisions.
Solution Approach 2:
The compilation technique performs preliminary analysis during the compilation phase to determine the optimal distribution of instructions across auxiliary processors. By pre-determining which instructions should execute on which processors based on resource connectivity and processor capabilities, the system avoids complex runtime scheduling decisions and achieves optimal performance without increasing runtime complexity.
2Power
If instructions are distributed across multiple auxiliary processors, then bandwidth utilization for target resources increases, but determining the most suitable processor for each instruction increases compilation complexity
Solution Approach 1:
The compilation technique applies local quality by analyzing the specific resource connectivity characteristics of each auxiliary processor. The compiler identifies which processors have direct connectivity or higher bandwidth to specific resources, and assigns instructions targeting those resources to the locally-optimal processors. This localized optimization maximizes bandwidth utilization without requiring global reconfiguration.
Solution Approach 2:
The compilation technique changes parameters by considering multiple factors including processor capabilities, resource connectivity, and instruction characteristics. The compiler evaluates these parameters to determine the optimal processor for each instruction, transforming the compilation process from a simple distribution task to a parameter-driven optimization process that maximizes bandwidth utilization.
3Loss of time
If instructions target resources with affinity to specific auxiliary processors, then latency is reduced, but the compilation process must analyze processor-resource relationships increasing complexity
Solution Approach 1:
The compilation technique performs preliminary analysis of processor-resource affinity relationships during the compilation phase. By pre-determining which auxiliary processors have direct connectivity or lower latency to specific resources, the compiler can assign instructions to the optimal processors without runtime overhead. This preliminary action reduces execution latency while keeping runtime complexity low.
Solution Approach 2:
The compilation technique acts as an intermediary that bridges the gap between high-level instruction code and the physical processor-resource architecture. The compiler analyzes processor-resource relationships and transforms instructions into processor-specific forms that exploit affinity relationships, reducing latency without requiring the runtime system to perform complex affinity analysis.
Data Source
AI summary
A compilation technique is provided. The technique includes including a first instruction into a first executable for a first auxiliary processor, wherein the first instruction specifies execution by the first auxiliary processor; and including a second instruction into the first executable, wherein the second instruction targets resources that have affinity with the first auxiliary processor.