Compiler Cache Line Alignment for GPU Vector Data
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Solution Overview
Problem
Graphics processing units (GPUs) face inefficiencies in handling large vector types due to limitations in cache line sizes, leading to scattered writes and reduced cache friendliness, which negatively impacts performance in scatter/gather workloads.
Innovation Solution
A compiler-based optimization that rearranges data structures to fit within a single cache line, converting large vector types into smaller components that can be efficiently stored and retrieved, using address shuffling to ensure all data fits within a cache line, thereby improving cache friendliness and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large vector types are used in OpenCL kernels, then the ability to process more data per operation is improved, but the data scattering to random addresses causes cache inefficiency and performance degradation
Solution Approach 1:
The patent segments large vector data structures into smaller components that can be efficiently mapped to cache line boundaries. By dividing the int16 vector into four int4 vectors, each fitting within a cache line, the system maintains both the ability to process large amounts of data and the cache efficiency required for high performance.
Solution Approach 2:
The patent transforms the data organization from a single large vector spanning multiple cache lines into a multi-dimensional structure where data is arranged to fit within cache line boundaries. This dimensional reorganization allows the compiler to generate more efficient code by operating on cache-friendly data layouts.
2Loss of energy
If the graphics processing unit handles smaller vector sizes, then cache line efficiency is improved, but the number of instructions required to process the same data increases
Solution Approach 1:
The patent merges multiple small vector operations into a unified compilation scheme that handles the entire large vector in a coordinated manner. By combining four int4 store instructions into a single compilation unit that processes an int16 vector, the system achieves cache efficiency without requiring manual intervention for each small vector operation.
Solution Approach 2:
The patent introduces a compiler intermediary that automatically performs the transformation from user-level large vector operations to hardware-friendly small vector operations. This intermediary layer handles the complexity of generating multiple store instructions and managing cache line alignment, making the process transparent to the application developer.
3Speed
If implicit vectorization is used to parallelize kernels, then processing speed is improved, but the translation of user-level vectors into SIMD lanes creates scattering issues
Solution Approach 1:
The patent performs preliminary reorganization of data structures during compilation, before the kernel executes. By pre-aligning vector data to cache line boundaries and organizing the int16 vector into four cache-friendly int4 components, the system ensures that subsequent parallel execution does not suffer from cache scattering issues.
Data Source
AI summary
An input data structure of a first size may be converted to a plurality of data structures of a second size smaller than the first size. The data structures of the second size are realigned such that each of the plurality of data structures fits in one cache line. The realigned data structures are compiled for use in a vector machine.