Compiler Cache Allocation via Partition Maps

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Solution Overview

Problem

In multicore processor systems, shared cache resources are inefficiently allocated due to conflicting demands from processor cores, leading to sub-optimal performance and increased latency and power consumption, especially for applications with varying memory usage patterns.

Innovation Solution

A compiler-generated map is created to dynamically partition the shared cache based on the execution characteristics of individual applications, allowing for optimized allocation of cache resources and reducing interference among processor cores.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a shared cache is used by multiple processor cores, then cache resource utilization is improved, but cache conflict and processor efficiency deteriorate

Engineering Contradiction:
Improvecache resource utilizationVSAvoidprocessor efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The shared cache is segmented into multiple partitions, with each partition dedicated to a specific processor core or application. The cache management unit maintains a partition map that tracks which core can access which cache partition, eliminating conflicts while maintaining high resource utilization through compiler-directed placement of data structures in appropriate partitions.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If cache space is shared equally among applications, then fairness is improved, but allocation optimality deteriorates

Engineering Contradiction:
Improvefairness of cache allocationVSAvoidallocation optimality
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

Different cache partitions are allocated to different applications based on their specific needs and characteristics. The compiler analyzes each application's data access patterns and directs data structures to specific cache partitions where they will be most effective, providing locally optimized allocation rather than uniform distribution.

Inventive Principle:
Principle #3Local quality

3Productivity

If more cache space is allocated to an application, then performance is improved, but other applications suffer from cache starvation

Engineering Contradiction:
Improveapplication performanceVSAvoidavailable cache for other applications
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The cache is divided into fixed partitions that guarantee minimum resource allocation to each application. This segmentation prevents any single application from monopolizing cache space while ensuring each application has dedicated cache resources, resolving the trade-off between performance and resource availability for other applications.

Inventive Principle:
Principle #1Segmentation

4Loss of time

If cache conflicts are reduced through partitioning, then latency is reduced, but cache management complexity increases

Engineering Contradiction:
Improvecache access latencyVSAvoidcache management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

A cache management unit acts as an intermediary between processor cores and the partitioned cache. It maintains a partition map and handles address translation and partition management, isolating the complexity from the processor cores themselves while enabling efficient conflict-free cache access.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8131970B2Compiler based cache allocation
Publication Date: 2012.03.06 MERCURY KINGDOM ASSETS LIMITED
  • US8131970B2 patent drawing
  • US8131970B2 patent drawing
  • US8131970B2 patent drawing

AI summary

Techniques a generally described for creating a compiler determined map for the allocation of memory space within a cache. An example computing system is disclosed having a multicore processor with a plurality of processor cores. At least one cache may be accessible to at least two of the plurality of processor cores. A compiler determined map may separately allocate a memory space to threads of execution processed by the processor cores.