Compiler Cache Management for Multiprocessor Coherency

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Solution Overview

Problem

Multiprocessor systems face challenges in maintaining data coherency due to issues like stale data and false sharing, which are exacerbated by the need for costly hardware-based coherency control and increased overhead as the number of processors grows, leading to inefficiencies in memory access and processor operation.

Innovation Solution

A method is introduced where a compiler generates software-based cache manipulation code to manage cache states and prevent stale data and false sharing by using explicit commands like writeback, self-invalidate, and purge, and aligns variables to avoid cache line conflicts, thereby eliminating the need for hardware-based coherency control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If hardware-based coherency control is implemented, then data coherency is maintained, but device complexity and cost increase

Engineering Contradiction:

Improvedata coherencyVSAvoidhardware complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces hardware-based coherency control mechanisms with software-based control. The compiler generates explicit cache manipulation code (writeback, self-invalidate, purge commands) that runs on the processors to maintain cache coherency, eliminating the need for complex hardware coherency control logic and reducing overall device complexity while maintaining data coherency

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces cache manipulation commands as an intermediary layer between the processor and cache memory. These commands (writeback, self-invalidate, purge) act as mediators that coordinate cache operations across multiple processors, enabling software-based coherency control without requiring direct hardware intervention

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If hardware-based coherency control is implemented, then data coherency is maintained, but manufacturing cost increases

Engineering Contradiction:

Improvedata coherencyVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent substitutes hardware coherency control circuits with software solutions compiled into executable code. This elimination of specialized hardware components reduces manufacturing costs while maintaining the essential coherency control functionality through compiler-generated cache manipulation commands

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If the number of processors is increased, then processing power is improved, but coherency control overhead increases

Engineering Contradiction:

Improveprocessing powerVSAvoidcoherency control overhead

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent replaces hardware-based coherency control with software-based control, which reduces the overhead associated with increasing processor counts. The compiler-generated code efficiently manages cache operations without requiring complex hardware coordination, allowing the system to scale to more processors with minimal additional overhead

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent implements self-service coherency control where each processor independently executes cache manipulation commands generated by the compiler. This eliminates the need for centralized hardware control that would become a bottleneck with increased processor counts, allowing each processor to manage its own cache coherency autonomously

Inventive Principle:

Principle #25Self-service

4Reliability

If hardware-based coherency control is implemented, then data coherency is maintained, but power consumption increases

Engineering Contradiction:

Improvedata coherencyVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent substitutes energy-consuming hardware coherency control circuits with software-based control that executes on existing processor logic. This eliminates the continuous power consumption of hardware coherency control mechanisms while maintaining coherency through compiler-generated cache manipulation commands that only execute when needed

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentEP3486767B1Method of managing a storage area of a memory in a multiprocessor system

Publication Date: 2020.07.22 WASEDA UNIV

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Figure 3A~3B

AI summary

It is provided a method of generating a code by a compiler, including the steps of: analyzing a program executed by a processor; analyzing data necessary to execute respective tasks included in a program; determining whether a boundary of the data used by divided tasks is consistent with a management unit of a cache memory based on results of the analyzing; and generating a code for providing a non-cacheable area from which the data to be stored in the management unit including the boundary is not temporarily stored into the cache memory and a code for storing an arithmetic processing result stored in the management unit including the boundary into a non-cacheable area in a case where it is determined that the boundary of the data used by the divided tasks is not consistent with the management unit of the cache memory.