Compiler Color Selection Schemes for Storage Allocation
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Solution Overview
Problem
Current storage allocation techniques for integrated circuit devices face challenges in optimizing memory usage and parallelism, as they often rely on graph-coloring allocation methods that do not effectively balance the number of colors (registers or memory locations) with the need for increased parallelism, leading to inefficiencies in execution time and memory management, especially when handling complex computations like those in artificial neural networks.
Innovation Solution
The proposed solution involves a compiler-driven approach that constructs an interference graph to determine memory location assignments through color selection schemes, which include simplification and rebuilding processes to optimize memory allocation, allowing for the reuse and rotation of colors to balance parallelism and memory usage, thereby improving the efficiency of storage allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If graph-coloring allocation methods are used to assign memory locations, then memory usage is managed, but the number of colors (registers or memory locations) increases without effectively balancing parallelism needs
Solution Approach 1:
The patent applies dynamics by making the color selection process adaptive and iterative. The system dynamically adjusts the number of colors and allocation strategy based on the interference graph's characteristics and the available register file size. The algorithm iterates through different color assignment strategies, evaluating their impact on parallelism and memory pressure, thereby dynamically optimizing the balance between resource usage and execution efficiency.
Solution Approach 2:
The patent changes key parameters including the number of colors, color assignment strategies, and allocation thresholds based on the specific computation being optimized. By adjusting these parameters adaptively, the system can optimize memory usage for different workloads and hardware configurations, resolving the contradiction between quantity of resources and productivity.
2Productivity
If more colors are allocated to increase parallelism, then execution parallelism improves, but memory pressure and execution cycles increase
Solution Approach 1:
The patent applies partial action by selectively assigning colors only where necessary based on interference analysis. Instead of uniformly allocating maximum colors to all variables, the system identifies critical variables that truly require separate memory locations and assigns colors only to those. This partial allocation strategy reduces overall memory pressure while maintaining sufficient parallelism for execution.
Solution Approach 2:
The system creates multiple color assignments (copies of the color palette) that can be applied to different sets of variables. By managing multiple color assignments simultaneously and strategically, the system achieves higher parallelism where needed while reusing colors elsewhere, thereby reducing total memory usage.
3Ease of manufacture
If conventional storage allocation is used, then implementation is simple, but execution time and memory management efficiency deteriorate
Solution Approach 1:
The patent applies preliminary action by performing interference analysis and color selection during the compilation phase rather than at runtime. The system pre-determines optimal memory location assignments based on the program's structure and data dependencies, creating an optimized storage allocation plan before execution begins. This preliminary optimization reduces execution time without significantly complicating the overall system architecture.
Data Source
AI summary
A compiler-implemented technique for performing a storage allocation is described. Computer code to be converted into machine instructions for execution on an integrated circuit device is received. The integrated circuit device includes a memory having a set of memory locations. Based on the computer code, a set of values that are to be stored on the integrated circuit device are determined. An interference graph that includes the set of values and a set of interferences is constructed. While traversing the interference graph, a set of memory location assignments are generated by assigning the set of values to the set of memory locations in accordance with one or more color selection schemes.