Compiler-Configured Compute Unit Staggering for Inductive Voltage Droop
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Solution Overview
Problem
Integrated circuits experience operational failures due to inductive-induced voltage droop and overshoot caused by large changes in current draw, which traditional solutions like clock stretching negatively impact performance and incur additional costs.
Innovation Solution
A compiler generates configuration information to statically reconfigure an integrated circuit, enforcing a paradigm where compute units are staggered in time to mitigate current ramp changes, using control circuitry to manage current draw and prevent voltage fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock stretching is used to reduce current ramp rate, then voltage droop is mitigated, but performance and productivity deteriorate
Solution Approach 1:
The compute units are segmented into multiple groups, where each group is assigned a unique identifier. By controlling the activation of different groups in a staggered manner, the current ramp rate is reduced without requiring clock stretching, thus maintaining both voltage stability and performance
Solution Approach 2:
The compiler performs preliminary analysis of the computational graph to identify compute units that can be safely grouped and staggered. Configuration information is generated in advance to enforce the staggered activation paradigm, preventing voltage droop before it occurs rather than reacting to it
2Productivity
If compute units are activated simultaneously to maximize throughput, then productivity improves, but inductive-induced voltage droop increases
Solution Approach 1:
Instead of simultaneous activation, compute unit groups are activated in periodic waves with controlled intervals. The compiler enforces a paradigm where groups are activated sequentially with staggered timing, creating a periodic activation pattern that limits current ramp rate while maintaining high overall throughput
Solution Approach 2:
The activation timing parameter of compute units is changed from simultaneous to staggered. By modifying the time parameter of activation for different compute unit groups, the current draw profile is transformed to have a gentler slope, reducing inductive voltage droop while preserving computational throughput
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the negative impact of inductive-induced voltage droop and overshoot, maintaining performance without the drawbacks of traditional methods.
Implementation Method 1
the voltage drop across an inductive load is the product of the inductance of the load and the time rate of change of the current drawn through the inductive loads, which may be expressed in equation (1) below in which L is the inductance of the load and di/dt is the first derivative of the current with respect to time through the load
Data Source
AI summary
A method includes analyzing a dataflow graph to generate configuration information loadable into an integrated circuit. The dataflow graph specifies operations to be performed and data dependencies between the operations. The configuration information is usable by the integrated circuit to configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow graph, control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units, and control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit.