Compiler Configuring Hardware Computational Units for Network Packet Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Network interface devices face challenges in efficiently processing and configuring hardware to handle data packets, particularly in optimizing data streams and reducing the complexity of program branches, while maintaining performance and throughput.
Innovation Solution
A compiler method that configures hardware in network interface devices by defining computational units to process data packets as streams of words, using buffers for data storage, converging common accesses, and optimizing packet and map accesses, while also reducing program branches through conditional execution and switch combinations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If computational units process data packets as streams of words with multiple buffers, then data processing capability is improved, but device complexity increases
Solution Approach 1:
The data processing system is divided into multiple computational units, each handling specific portions of packet data streams. Each computational unit processes words independently, allowing parallel operation and improving overall throughput without requiring a single complex processing unit.
Solution Approach 2:
Buffers are introduced as intermediary components between computational units to temporarily store data words. This allows computational units to operate independently without direct synchronization, simplifying the control logic while maintaining high data flow efficiency.
2Device complexity
If multiple accesses are converged into single access operations, then hardware complexity is reduced, but processing time may increase
Solution Approach 1:
Multiple packet accesses that target the same memory location are merged into single access operations. The compiler identifies redundant accesses within a convergence window and combines them, reducing the total number of memory access operations and simplifying hardware requirements.
Solution Approach 2:
The compiler performs preliminary analysis of access patterns during the compilation phase to identify and merge redundant accesses before code execution. This static analysis allows the system to optimize access patterns without adding runtime overhead.
3Device complexity
If program branches are reduced through conditional execution, then device complexity is reduced, but adaptability decreases
Solution Approach 1:
The system uses dynamic conditional execution where computational units can be enabled or disabled based on runtime conditions. This allows the hardware to adapt to different packet processing requirements without requiring multiple fixed architectural configurations, maintaining flexibility while reducing structural complexity.
Data Source
AI summary
A method comprises compiling, by a compiler, a received program to provide a compiler output for configuring hardware to implement the received program. The received program relate to packets of data in a memory. The compiling comprising defining by the compiler output a plurality of computational units in the hardware, each of the computational units being configured to receive a packet of data as a stream of words and between a first and a second of the computational units, a first buffer for storing words of a packet and a second buffer for storing data output by the first computational unit.