Compiler Transforming Control Flow to Data Flow Code

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Solution Overview

Problem

Computing systems with control flow architectures face challenges in parallel processing, as instructions may execute before their data dependencies are updated, leading to inefficiencies, especially when trying to implement parallel processing.

Innovation Solution

A compiler is enhanced to convert control flow code into optimized data flow code, using a spatial accelerator that combines hybrid data flow and control flow models, allowing for efficient execution on a spatial accelerator by converting control flow code to data flow code, optimizing for parallel processing and energy efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If control flow architecture is used to execute instructions in a defined order, then program structure is maintained, but parallel processing efficiency deteriorates due to instructions executing before their data dependencies are updated

Engineering Contradiction:

Improveparallel processing efficiencyVSAvoiddata dependency correctness

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent inverts the traditional control flow execution model by implementing a data flow architecture where instruction execution is determined by data availability rather than program order. The execution unit executes instructions as soon as their input operands are ready, reversing the conventional approach where the program counter dictates execution order regardless of data readiness.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent introduces dynamic instruction execution where the execution flow adapts based on data readiness. The execution unit dynamically selects which instructions to execute next based on whether their input operands are available, creating a flexible execution model that can parallelize operations when data dependencies allow.

Inventive Principle:

Principle #15Dynamics

2Productivity

If data flow architecture is used to execute instructions based on operand availability, then parallel processing capability is improved, but device complexity increases due to the need for data dependency tracking

Engineering Contradiction:

Improveparallel processing capabilityVSAvoiddata dependency tracking mechanism

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces an operand address generation unit as an intermediary component that manages data dependency tracking. This unit generates operand addresses and provides input data to the execution unit, acting as a mediator between the instruction queue and the execution resources, thereby simplifying the overall data flow management.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the instruction execution process into distinct functional units: an instruction queue that holds pending operations, an execution unit that performs computations, and an operand address generation unit that manages data flow. This segmentation allows each component to specialize in its function, reducing overall system complexity.

Inventive Principle:

Principle #1Segmentation

3Ease of manufacture

If traditional compiler generates control flow code, then code structure is simple, but execution efficiency on parallel architectures deteriorates

Engineering Contradiction:

Improvecode generation simplicityVSAvoidexecution efficiency on parallel architectures

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The patent transforms the code representation by changing parameters from control flow variables to data flow descriptors. The intermediate representation uses data flow instructions that explicitly specify input and output operands, enabling the compiler to generate code optimized for data flow execution without significantly increasing code complexity.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent introduces an intermediate representation (IR) as a mediator between the source code and the target machine code. This IR uses data flow instructions that capture both the computational logic and the data dependencies, allowing the compiler to optimize for parallel execution while maintaining a manageable code representation.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10402176B2Methods and apparatus to compile code to generate data flow code

Publication Date: 2019.09.03 INTEL CORP

AI summary

Methods, apparatus, systems and articles of manufacture to compiler compile code to generate dataflow code are described. An example compiler apparatus includes an intermediate representation transformer to transform input software code to intermediate representation code; an instruction selector to insert machine instructions of a target execution platform in the intermediate representation code to generate machine intermediate representation code; and a target machine transformer to: convert a portion of the machine intermediate representation code to dataflow code to generate dataflow intermediate representation code; and allocate registers within the dataflow intermediate representation code.