Compiler Dependency Analysis Using Partition Structures
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Solution Overview
Problem
Conventional compilers face inefficiencies in determining instruction dependencies due to conservative memory resource handling and the performance degradation of N-square algorithms as problem size increases, leading to suboptimal instruction reordering and compilation speed.
Innovation Solution
A method that involves mapping memory elements to a partition structure with disjunct partition elements representing overlaps, allowing for a look-up operation to determine object dependencies and subsequently instruction dependencies, thereby reducing the problem size and enabling fine-grained memory element-level analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the compiler treats each memory resource as a single entity and considers each instruction to affect the entirety of each memory resource, then the dependency analysis is conservative and simple, but the compiler is unable to consider all valid reorderings and cannot determine the optimal reordering
Solution Approach 1:
The patent segments memory resources into individual memory elements (bits) and introduces partition elements that group scattered memory elements accessed by instructions. This segmentation allows the compiler to analyze dependencies at the fine-grained memory element level rather than treating entire memory resources as single entities, enabling identification of valid reorderings that were previously missed due to conservative whole-resource analysis.
2Productivity
If the compiler splits each memory resource into separate memory resources representing single elements and constructs a dependency graph, then the conservatism is reduced and fine-grained analysis is enabled, but the N-square algorithm performance degrades as problem size increases
Solution Approach 1:
The patent merges scattered memory elements that are accessed by the same instruction into partition elements. Instead of creating separate dependency graph nodes for each individual memory element, the patent combines them into partition elements that represent groups of memory elements with similar access patterns. This merging reduces the problem size from O(N) individual elements to O(P) partition elements where P < N, thereby reducing the N-square algorithm complexity and compilation time while maintaining fine-grained analysis capabilities.
3Loss of time
If the compiler uses conservative dependency analysis treating instructions as affecting entire memory resources, then compilation speed is maintained, but the execution speed optimization is limited due to inability to consider all valid reorderings
Solution Approach 1:
The patent introduces a new dimension of analysis by creating partition elements that represent groups of memory elements. This additional layer of abstraction allows the compiler to maintain efficient compilation speed while enabling fine-grained dependency analysis. The partition elements serve as an intermediate representation that bridges the gap between coarse-grained whole-resource analysis and fine-grained individual-element analysis, allowing optimal instruction reordering to be identified without excessive compilation time.
Data Source
AI summary
One embodiment sets forth a method for efficiently determining memory resource dependencies between instructions included in a software application. For each instruction, a dependency analyzer uses overlapping search techniques to identify one or more overlaps between the memory elements included in the current instruction and the memory elements included in previous instructions. The dependency analyzer then maps objects included in the instructions to a set of partition elements wherein each partition element represents a set of memory elements that are functionally equivalent for dependency analysis. Subsequently, the dependency analyzer uses the set of partition elements to determine memory dependencies between the instructions at the memory element level. Advantageously, the disclosed techniques enable the compiler to retain an acceptable compilation speed while tuning the instruction ordering at a fine-grained memory element level, thereby increasing the speed at which the processor may execute the software application.