Compiler-Generated Flush Instructions for Cache Coherence
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Solution Overview
Problem
High-performance computing (HPC) systems face data transfer latency issues due to cache coherence problems between general-purpose processors and function accelerators, leading to reduced system throughput in shared memory spaces.
Innovation Solution
A distributed cache system is generated through compiler-directed cache coherence logic, where high-level language source code is compiled into intermediate language with flush instructions to optimize cache flushing and overlap data transfer with processing, ensuring coherent memory views across the system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is stored in distributed caches on function accelerators, then data processing speed is improved, but cache coherence latency increases
Solution Approach 1:
The compiler inserts flush instructions at strategically determined points in the intermediate language program, performing cache flushing actions in advance or at optimal moments before data coherence issues arise, rather than waiting for latency problems to manifest
Solution Approach 2:
The patent introduces a compiler-generated intermediate language program as a mediator between the high-level language source code and the hardware implementation. This intermediate language includes explicit flush instructions that coordinate cache operations, acting as an intermediary control mechanism to manage coherence between distributed caches and main memory
2Reliability
If compiler generates flush instructions for cache coherence, then memory coherence is improved, but system complexity increases
Solution Approach 1:
The compiler automatically performs the complex task of analyzing the intermediate language program, determining optimal cache flush points, and inserting appropriate flush instructions without requiring manual intervention. The system serves itself by having the compiler generate its own coherence management code
Solution Approach 2:
The intermediate language program serves as an intermediary representation that captures both the computational logic and the cache coherence requirements. This intermediate form allows the compiler to systematically analyze and generate flush instructions, bridging the gap between high-level algorithm specification and low-level hardware control
3Productivity
If data transfer is overlapped with processing, then system throughput is improved, but data transfer latency increases
Solution Approach 1:
The patent enables continuous useful action by overlapping data transfer operations with processing operations through pipeline parallelism. While data is being transferred from caches to main memory via flush instructions, the function accelerator continues processing other data, ensuring that the system remains productive throughout the transfer latency period
Data Source
AI summary
Approaches for generating and operating an electronic system. High-level language (HLL) source code is compiled into equivalent intermediate language program code. The compilation determines a plurality of caches for storing data referenced by the HLL source. Flush instructions are inserted in the intermediate language program. Each flush instruction references one of caches and is inserted in the intermediate language program immediately following an instruction that is last to write to that cache. The intermediate language program is translated into a hardware description that specifies the plurality of caches, circuits for processing data in the caches, and for each of the caches a flush interface that initiates writing data from the cache to a main memory in response to a flush signal. The timing of the respective flush signal is determined based on placement of one of the one or more flush instructions in the intermediate language program.