Compiler Generating Compute Kernels for Array Instructions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Efficient execution of array instructions on heterogeneous and parallel computing systems is challenging due to the complexity of mapping workload chunks to available resources, leading to increased maintenance efforts and incompatibilities across diverse hardware setups.
Innovation Solution
A computer-implemented method that generates a first program segment by determining runtime size information and including array instructions based on function meta information and hardware information, allowing for the compilation of a compute kernel executable on processing units, thereby optimizing workload distribution and execution efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manual decision making by the programmer is used to target specific processors for data processing, then execution efficiency on specific hardware can be optimized, but maintenance effort increases and incompatibilities arise across diverse hardware setups
Solution Approach 1:
The compiler automatically performs processor selection and code adaptation without requiring manual programmer intervention. The system self-adjusts to different hardware configurations by analyzing hardware information and runtime size information, generating optimized code for the target processor automatically.
Solution Approach 2:
The compiler dynamically adjusts code generation parameters based on detected hardware information and runtime characteristics. By changing compilation parameters according to the target processor's capabilities, the system achieves optimal execution efficiency across diverse hardware without manual reconfiguration.
2Loss of time
If the compiler targets specific processing units with customized code generation, then execution time is reduced, but device complexity and difficulty of adapting to heterogeneous hardware increases
Solution Approach 1:
The compiler employs dynamic code generation that adapts to the target processor's characteristics at compile time. By dynamically selecting optimization strategies and code patterns based on detected hardware information, the compiler reduces execution time without requiring manual customization for each processor type.
Solution Approach 2:
The code generation process is segmented into modular phases: hardware information detection, runtime size information determination, and targeted code generation. This segmentation allows the compiler to systematically handle different processor types through standardized procedures, reducing overall complexity.
3Productivity
If heterogeneous computing resources are utilized for parallel processing, then productivity and energy efficiency improve, but the complexity of mapping workload chunks to available resources increases significantly
Solution Approach 1:
The compiler implements a universal code generation framework that can target multiple processor types and heterogeneous computing resources through a single compilation process. By designing the system to be hardware-agnostic at the interface level while generating specialized code internally, the compiler simplifies workload mapping across diverse parallel computing resources.
4Adaptability or versatility
If manual adaptation of user code is performed for different computing architectures, then compatibility across hardware platforms is achieved, but development cycles are extended and product deliveries are delayed
Solution Approach 1:
The compiler acts as an intermediary layer between user code and diverse computing architectures. By translating high-level array instructions into processor-specific optimizations automatically, the compiler ensures hardware compatibility without requiring programmers to manually adapt code for different platforms, thus shortening development cycles.
Data Source
AI summary
A computer-implemented method includes receiving a program code comprising a sequence of array instructions for at least one input array data structure storing multiple elements of a respective common data type, and function meta information, FMI. The FMI allow for determining an output size information of an output of each array instruction of the sequence of array instructions for an input size information of the at least one input array data structure. The method includes receiving hardware information of a processing unit, compiling, based on the first program segment, the runtime size information and the hardware information, a first compute kernel which is executable on the processing unit; and executing the first compute kernel on the processing unit using the runtime instance of the at least one input array data structure as input.