Compiler Instruction Scheduling via Register Pressure Sensitivity
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Solution Overview
Problem
Existing compiler optimization techniques often conflict between instruction scheduling and register allocation, leading to increased register pressure and inefficiency due to the frequent rearrangement of instructions without considering their overall impact on register allocation, resulting in higher spilling rates and reduced compiler performance.
Innovation Solution
A mechanism for instruction scheduling that takes into account both current and potential register pressures at various program points, performing preliminary register pressure minimization and calculating register pressures to optimize instruction placement and reduce register pressure, thereby improving compiler optimization and generated code performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instruction scheduling is performed frequently to increase processor instruction throughput, then instruction throughput is improved, but register pressure on subsequent scheduling points increases leading to more spills
Solution Approach 1:
The patent performs preliminary register pressure minimization before instruction scheduling by calculating register pressures at all program points and reordering instructions to minimize register pressure in advance. This preliminary action allows subsequent instruction scheduling to proceed with lower baseline register pressure, enabling more frequent scheduling without proportionally increasing spill operations.
Solution Approach 2:
The patent calculates register pressures at each program point and uses this feedback information to guide instruction scheduling decisions. The register pressure calculations provide real-time feedback about the state of register usage, allowing the scheduler to make informed decisions about instruction reordering that balance throughput improvement with register pressure management.
2Ease of operation
If instruction scheduling rearranges instructions without considering overall impact on register allocation, then instruction scheduling is simplified and faster, but register allocation efficiency deteriorates
Solution Approach 1:
The patent performs preliminary register pressure minimization by calculating register pressures at all program points before instruction scheduling. This preliminary calculation of register pressures provides the scheduler with advance knowledge of register usage patterns, enabling it to make efficient scheduling decisions without complex iterative analysis during the scheduling phase itself.
Solution Approach 2:
The patent changes the parameter consideration in instruction scheduling from purely timing and dependency constraints to include register pressure sensitivity. By incorporating register pressure as a scheduling parameter, the patent enables the scheduler to balance instruction reordering benefits against register allocation costs, improving overall compiler optimization efficiency.
3Device complexity
If the number of available processor registers is limited by architectural design, then processor structure is simplified, but spilling increases when processing large numbers of program variables
Solution Approach 1:
The patent performs preliminary register pressure minimization by calculating register pressures at all program points and reordering instructions to minimize register pressure before execution. This preliminary reordering reduces the frequency and cost of spill operations, compensating for the limited number of physical registers without requiring architectural changes.
Solution Approach 2:
The patent changes the approach to register allocation by introducing register pressure sensitivity as a dynamic parameter that guides instruction scheduling. Instead of statically allocating registers without regard to usage patterns, the patent dynamically adjusts instruction ordering based on calculated register pressures, reducing spill operations and their associated performance penalties.
Data Source
AI summary
A mechanism for performing instruction scheduling based on register pressure sensitivity is disclosed. A method of embodiments of the invention includes performing a preliminary register pressure minimization on program points during a compilation process of a software program running on a virtual machine of a computer system. The method further includes calculating a register pressure at each of the program points, detecting an instruction to be scheduled, and performing instruction scheduling of the instruction based on a current register pressure at a current scheduling point and potential register pressures at subsequent scheduling points.