Compiler Instrumentation for HLS Transaction-Accurate Simulation
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Solution Overview
Problem
High-level synthesis (HLS) circuit design simulation is time-consuming due to the need for converting HLL specifications into RTL specifications and subsequent RTL simulation, which requires significant computational resources and makes iterative debugging difficult.
Innovation Solution
Instrumenting the HLS kernel by replacing global address space accesses with calls to wrapper functions, generating a simulation kernel in assembly language that can be executed natively, thereby avoiding RTL conversion and improving simulation speed and debugging efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If HLL specification is converted to RTL specification for simulation, then functional verification is achieved, but simulation time and computational resources increase significantly
Solution Approach 1:
The patent segments the simulation process by creating a separate transaction-level simulation model that operates independently from the detailed RTL simulation. This model extracts and simulates only the critical transaction behaviors, allowing functional verification without requiring full RTL conversion and execution, thereby reducing simulation time while maintaining verification reliability.
Solution Approach 2:
The patent creates a simplified copy or abstraction of the RTL design at the transaction level. This transaction-level model replicates the essential functional behavior and interface characteristics of the original RTL design, enabling functional verification through simulation of the simplified model rather than the complex RTL implementation, thus reducing computational resources and simulation time.
2Reliability
If RTL simulation is performed to verify circuit design, then design functionality is confirmed, but debugging capability is reduced
Solution Approach 1:
The patent introduces a transaction-level simulation model as an intermediary between the high-level design specification and the detailed RTL implementation. This intermediary model maintains the semantic meaning and debugging capabilities of the high-level language while providing functional verification, allowing designers to debug using familiar high-level constructs rather than struggling with low-level RTL simulation limitations.
3Manufacturing precision
If iterative modifications are made to HLL specification and re-simulated, then design optimization is achieved, but total development time increases
Solution Approach 1:
The patent performs preliminary extraction of transaction-level behavior from the HLL specification before iterative optimization begins. This pre-extracted model serves as a fast simulation target that can be quickly re-simulated during iterative design optimization, avoiding the need to re-convert and re-simulate full RTL specifications with each design iteration, thus accelerating the optimization process while maintaining design precision.
Data Source
AI summary
Compiling a high-level synthesis circuit design for simulation includes analyzing, using computer hardware, a kernel specified in a high-level language to detect pointers therein. A determination is made as to which of the pointers are global address space pointers referencing a global address space. The kernel is instrumented by replacing accesses in the kernel to the global address space with calls to wrapper functions for performing the accesses. A simulation kernel is generated that specifies an assembly language version of the kernel as instrumented.