Compiler Loop Parallelization via Dependency Elimination
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Solution Overview
Problem
Existing computer architectures face performance constraints due to loop-carried dependencies, which prevent parallel execution of loops on coarse-grained reconfigurable array (CGRA) processors, limiting their ability to utilize hardware multithreading and SIMD capabilities.
Innovation Solution
A method to identify and eliminate loop-carried dependencies by linking their patterns with those of non-loop-carried variables, using techniques such as pattern analysis and substitution with logical or mathematical operations, allowing loops to be executed in parallel across multiple processing elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If loop-carried dependencies are present in the code, then the code correctly implements sequential logic, but parallel execution on CGRA processors is prevented
Solution Approach 1:
The patent extracts loop-carried dependency variables from the sequential loop structure and creates separate compute kernels for each iteration. By taking out the dependency relationships and representing them as data flow patterns, the loop can be parallelized across multiple processing elements in the CGRA architecture.
Solution Approach 2:
The patent segments the sequential loop into multiple independent compute kernels, where each kernel represents a specific iteration or set of iterations. This segmentation allows each kernel to be executed in parallel on different processing elements, transforming sequential execution into parallel execution while maintaining the original computational logic.
2Productivity
If loop-carried dependencies exist, then sequential execution is straightforward, but hardware multithreading and SIMD capabilities cannot be utilized
Solution Approach 1:
The patent introduces intermediate data structures and communication mechanisms that mediate between the sequential loop logic and parallel hardware execution. These intermediaries include data flow graphs, kernel interfaces, and synchronization primitives that ensure correct data dependency handling while enabling parallel execution on CGRA processors with multithreading and SIMD capabilities.
3Reliability
If the loop is executed sequentially to maintain dependency correctness, then execution accuracy is ensured, but performance is constrained
Solution Approach 1:
The patent creates multiple copies of the loop body as separate compute kernels, where each copy processes a specific iteration or data subset. These copied kernels are executed in parallel on different processing elements, maintaining the original computational logic and dependency relationships while achieving speedup through parallel execution. The copying approach preserves execution accuracy by ensuring each kernel correctly implements the original loop semantics.
Data Source
AI summary
Devices and techniques for parallelizing loops that have loop-dependent variables are described herein. A system includes a processing device; and a memory device configured to store instructions, which when executed by the processing device, cause the processing device to perform operations comprising: accessing, by a compiler executing on a processing device, a computer code listing; determining that the computer code listing includes a loop with a loop-carried dependency variable; optimizing the loop for parallel execution by removing the loop-carried dependency variable; and compiling the computer code listing into executable software code with the loop executable in parallel in hardware.