Compiler Loop Transformation for Store-Fetch Interlock Prevention

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Solution Overview

Problem

Existing compiler optimization methods for loops with store and load commands result in performance degradation due to store fetch interlock (SFI) between preceding store and subsequent load commands, which cannot be effectively avoided by hardware or software alone.

Innovation Solution

A compiling method that transforms target loops into three distinct loop processes: a first loop to execute the store command ahead, a second loop to adjust access addresses, and a third loop to complete the remaining load commands, ensuring the store and load commands access different memory units to avoid SFI.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If store and load commands are executed in a loop process, then data processing is performed, but store fetch interlock causes performance degradation

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidperformance degradation
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The loop process is segmented into three distinct loop processes: first loop process executing store commands, second loop process executing both store and load commands, and third loop process executing load commands. This segmentation separates the store and load operations that were previously interleaved, preventing store fetch interlock while maintaining data processing functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first loop process executes store commands in advance before the load commands are executed in the third loop process. By performing the store action preliminarily and separately, the patent ensures that store and load operations do not interfere with each other, eliminating the performance degradation caused by store fetch interlock.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If store command is executed in advance to avoid SFI, then access address separation is achieved, but loop structure complexity increases

Engineering Contradiction:
ImproveSFI preventionVSAvoidloop structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The complex loop structure is managed by segmenting it into three clearly defined loop processes with distinct purposes. Each loop process handles specific commands (store-only, both store and load, load-only), making the complexity structured and manageable rather than chaotic, while reliably preventing SFI.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250335168A1Computer-readable recording medium storing compiling program and compiling method
Publication Date: 2025.10.30 FUJITSU LTD
  • US20250335168A1 patent drawing
  • US20250335168A1 patent drawing
  • US20250335168A1 patent drawing

AI summary

A recording medium stores a program causing a computer to execute a process including: detecting a target loop process that includes store and load commands subsequent to the store command; and changing the detected target loop process into a first loop process of executing the store command in advance for a first number of times among the number of iteration times of the target loop process, a second loop process of executing the store and load commands for a second number of times obtained by subtracting the first number of times from the number of iteration times after the first loop process, and a third loop process of executing the load command for the first number of times after the second loop process such that an access addresses of the store and load commands are not in the same access unit from a processor to a memory.